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hyb18t256400af hyb18t256800af HYB18T256160Af 256 mbit ddr2 sdram data sheet, v1.02, may 2004 memory products never stop thinking.
edition 2004-04-02 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 5/7/04. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 3 rev. 1.02 may 2004 rainer.weidlich@infineon.com features ? high performance: ? 1.8v 0.1v power supply 1.8 v 0.1v (sstl_18) compatible) i/o ? dram organisations with 4, 8 and 16 data in/outputs ? double data rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation ?cas latency: 3, 4 and 5 ? burst length: 4 and 8 speed sorts -5 ddr2 -400 -3.7 ddr2 -533 -3s ddr2 -667 -3 ddr2 -667 units bin (cl-trcd-trp) 3-3-3 4-4-4 5-5-5 4-4-4 tck max. clock frequency 200 266 333 mhz data rate 400 533 667 mb/s/pin cas latency (cl) 3 4 5 4 tck trcd 15 15 15 12 ns trp 15151512 ns tras 40 45 45 45 ns trc 55606057 ns ? differential clock inputs (ck and ck ) ? bi-directional, differential data strobes (dqs and dqs ) are transmitted / received with data. edge aligned with read data and center-aligned with write data ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ?posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on-die-termination (odt) for better signal quality. ? auto-precharge operation for read and write bursts ? auto-refresh, self-refresh and power saving power- down modes ? average refresh period 7.8s at a t case lower than 85 o c, 3.9s between 85 o c and 95 o c ? normal and weak strength data-output drivers ? 1k page size ? lead-freepackages: 60 pin fbga for x4 & x8 components 84 pin fbpa for x16 components 1.0 description the 256mb double-data-rate-2 (ddr2) drams are high- speed cmos double data rate 2 synchronous dram devices containing 268,435,456 bits and are internally config- ured as a quad-bank drams. the 256mb chip is organized as either 16mbit x 4 i/o x 4 bank, 8mbit x 8 i/o x 4 bank or 4mbit x 16 i/o x 4 bank device. these synchronous devices achieve high speed double-data-rate transfer rates of up to 667 mb/sec/pin for general applications. the chip is designed to comply with all key ddr2 dram key features: (1) posted cas with additive latency, (2) write latency = read latency -1, (3) normal and weak strength data- output driver, (4) off-chip driver (ocd) impedance adjust- ment and (5) an odt (on-die termination) function. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential (dqs, dqs ) pair in a source synchronous fashion. a 15 bit address bus is used to con- vey row, column and bank address information in a ras / cas multiplexing style. the ddr2 devices operate with a 1.8v +/-0.1v power supply and are available in fbga packages. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. . datasheet rev. 1.02 (05.04)
page 4 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 1.1 ordering information 1.2 pin description 1.2.1 x4 components part number cas latency clock (mhz) speed sort dram organisation package hyb18t256400af(l)-5 3, 4 & 5 200 ddr2-400 4 banks x 16 mbits x 4 60 pin fbga hyb18t256800af(l)-5 4 banks x 8 mbits x 8 60 pin fbga HYB18T256160Af(l)-5 4 banks x 4 mbits x 16 84 pin fbga hyb18t256400af(l)-3.7 4 & 5 266 ddr2-533 4 banks x 16 mbits x 4 60 pin fbga hyb18t256800af(l)-3.7 4 banks x 8 mbits x 8 60 pin fbga HYB18T256160Af(l)-3.7 4 banks x 4 mbits x 16 84 pin fbga hyb18t256400af(l)-3 4 & 5 333 ddr2-667 4 banks x 16 mbits x 4 60 pin fbga hyb18t256800af(l)-3 4 banks x 8 mbits x 8 60 pin fbga HYB18T256160Af(l)-3 4 banks x 4 mbits x 16 84 pin fbga hyb18t256400af(l)-3s 5 4 banks x 16 mbits x 4 60 pin fbga hyb18t256800af(l)-3s 4 banks x 8 mbits x 8 60 pin fbga HYB18T256160A(l)-3s 4 banks x 4 mbits x 16 84 pin fbga notes: 1) for product nomenclature see section 10 of this datasheet 2) versions with an ?l? in the part numbers are low power vers ions of the standard component with reduced idd6 self-refresh current. see section 6.1 for idd current specifications. 3) all fbga packages are lead-free. symbol function symbol function a0~a12 row address inputs dqs, dqs differential data strobes a0~a9,a11 column address inputs nc no connection (chip to pin) ba0, ba1 bank address inputs vdd supply voltage a10/ap column address input for auto-precharge vss ground cs chip select vddq supply voltage for dq ras row address strobe vssq ground for dqs cas column address strobe vddl supply voltage for dll we write enable vssdl ground for dll dq0~dq3 data inputs/outputs (x4) vref reference voltage for sstl inputs cke clock enable odt on die termination enable ck, ck differential clock inputs rfu reserved for future use dm data input mask nc not connected
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 5 rev. 1.02 may 2004 1.2.1 x8 components 1.2.3 x16 components symbol function symbol function a0~a12 row address inputs dqs, dqs differential data strobes a0~a9 column address inputs rdqs, rdqs differential read data strobes ba0, ba1 bank address inputs vdd supply voltage a10/ap column address input for auto-precharge vss ground cs chip select vddq supply voltage for dq ras row address strobe vssq ground for dqs cas column address strobe vddl supply voltage for dll we write enable vssdl ground for dll dq0~dq7 data inputs/outputs (x8) vref reference voltage for sstl inputs cke clock enable odt on die termination enable ck, ck differential clock inputs rfu reserved for future use dm data input mask nc not connected symbol function symbol function a0~a12 row address inputs ldqs,ldqs udqs,udqs differential data strobes a0~a8 column address inputs nc no connection (chip to pin) ba0, ba1 bank address inputs vdd supply voltage a10/ap column address input for auto-precharge vss ground cs chip select vddq supply voltage for dq ras row address strobe vssq ground for dqs cas column address strobe vddl supply voltage for dll we write enable vssdl ground for dll ldq0~7, udq0~7 data inputs/outputs vref reference voltage for sstl inputs cke clock enable odt on die termination enable ck, ck differential clock inputs rfu reserved for future use ldm, udm data input masks nc not connected
page 6 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 1.3 256mbit ddr2 addressing 1.4 package pinout & addressing 1.4.1 package pinout for x4 components, 60 pins, fbga package (top view) configuration 64mb x 4 32mb x 8 16mb x 16 # of banks 4 44 bank address ba0, ba1 ba0, ba1 ba0, ba1 auto-precharge a10 / ap a10 / ap a10 / ap row address a0 ~ a12 a0 ~ a12 a0 ~ a12 column address a0 ~ a9, a11 a0 ~ a9 a0 ~ a8 page length 2048 bits 1024 bits 512 bits page size 1024 (1kb) 1024 (1kb) 1024 (1kb) page length = 2 colbit, , page size in bytes = 2 colbits x org / 8 where colbits is the number of column address bits and org the number of i/o (dq) bits. 1 2 3 7 8 9 vdd nc vss a vssq dqs vddq nc vssq dm b dqs vssq nc vddq dq1 vddq c vddq dq0 vddq nc vssq dq3 d dq2 vssq nc vddl vref vss e vssdl ck vdd cke we f ras ck odt rfu ba0 ba1 g cas cs a10 a1 h a2 a0 vdd vss a3 a5 j a6 a4 a7 a9 k a11 a8 vss vdd a12 nc,(a14) l nc,(a15) nc,(a13) notes: 1) vddl and vssdl are power and ground for the dll.they are isolated on the device from vdd, vddq, vss and vssq. 2) nc, (a13), nc,(a14) and nc,(a15) are additional address pins for future genera- tion drams and are not connected on this component 3) ball position g1 ?rfu? will be used for ba2 on 1gbit memory densities and higher
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 7 rev. 1.02 may 2004 1.4.2 package pinout for x8 components, 60 pins, fbga package (top view) 1 2 3 7 8 9 vdd nu, rdqs vss a vssq dqs vddq dq6 vssq dm, rdqs b dqs vssq dq7 vddq dq1 vddq c vddq dq0 vddq dq4 vssq dq3 d dq2 vssq dq5 vddl vref vss e vssdl ck vdd cke we f ras ck odt rfu ba0 ba1 g cas cs a10 a1 h a2 a0 vdd vss a3 a5 j a6 a4 a7 a9 k a11 a8 vss vdd a12 nc,(a14) l nc,(a15) nc,(a13) notes: 1) rdqs / rdqs are enabled by emrs(1) command. 2) if rdqs / rdqs is enabled, the dm function is disabled 3) when enabled, rdqs & rdqs are used as strobe signals during reads. 4) vddl and vssdl are power and ground for the dll. they are isolated on the device from vdd, vddq, vss and vssq. 5) nc,(a13), nc,(a14) and nc,(a15) are additional address pins for future generation drams and are not connected on this component. 6) ball position g1 ?rfu? will be used for ba2 on 1gbit memory densities and higher
page 8 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 1.4.3 package pinout for x16 components 84 pins, fbga package (top view) 1 2 3 7 8 9 vdd nc vss a vssq udqs vddq udq6 vssq udm b udqs vssq udq7 vddq udq1 vddq c vddq udq0 vddq udq4 vssq dq3 d udq2 vssq udq5 vdd nc vss e vssq ldqs vddq ldq6 vssq ldm f ldqs vssq ldq7 vddq ldq1 vddq g vddq ldq0 vddq ldq4 vssq ldq3 h ldq2 vssq ldq5 vddl vref vss j vssdl ck vdd cke we k ras ck odt rfu ba0 ba1 l cas cs a10 a1 m a2 a0 vdd vss a3 a5 n a6 a4 a7 a9 p a11 a8 vss vdd a12 nc,(a14) r nc,(a15) nc,a13) notes: 1) udqs/udqs is data strobe for upper byte, ldqs/ldqs is data strobe for lower byte 2) udm is the data mask signal for the upper byte udq0~udq7, ldm is the data mask signal for the lower byte ldq0~ldq7 3) nc,(a13), nc, (a14) and nc, (a15) are additional address pins for future gener- ation drams and are not connected on this component. 4) ball position g1 ?rfu? will be used for ba2 on 1gbit memory densities and higher
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 9 rev. 1.02 may 2004 1.5 input/output functional description symbol type function ck, ck input clock: ck and ck are differential system clock inputs. all address and control inputs are sampled on the crossing of the positive edge of ck and negative edge of ck. output (read) data is referenced to the crossing of ck and ck (both direction of crossing) cke input clock enable: cke high activates and cke low deactivates intern al clock signals and device input buffers and out- put drivers. taking cke low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit and for self-refresh entry. input buffers excluding cke are disabled during self-refresh. cke is used asynchronously to detect self-refresh exit condition. self-refresh termination itself is synchronous. after vref has become stable during power-on and initiali- sation sequence, it must be maintained for proper operati on of the cke receiver. for proper self-refresh entry and exit, vref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during dower-down. cs input chip select: all command are masked when cs is registered high. cs provides for external rank selection on sys- tems with multiple memory ranks. c s is considered part of the command code. ras , cas , we input command inputs: r as , cas and we (along with cs ) define the command being entered dm, ldm, udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coinci- dent with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ldm and udm are the input mask signals for x16 compo- nents and control the lower or upper bytes. for x8 com ponents the data mask function is disabled, when rdqs / rqds are enabled by emrs(1) command. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an activate, read, write or precharge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs(1) cycle. a0 - a12 input address inputs: provides the row address for activate commands and the column address and auto-precharge bit a10 (=ap) for read/write commands to select one location out of the memory array in the respective bank. a10 (=ap) is sampled during a precharge command to determi ne whether the precharge applies to one bank (a10=low) or all banks (a10=high). if only one bank is to be prec harged, the bank is selected by ba0 and ba1. the address inputs also provide the op-code during mode register set commands. dqx, ldqx,udqx input/ output data inputs/output: bi-directional data bus. dq0~dq3 for x4 components, dq0~dq7 for x8 components, ldq0~ldq7 and udq0~udq7 for x16 components dqs, (dqs ) ldqs, (ldqs ), udqs,(udqs ) input/ output data strobe: output with read data, input with write data. edge al igned with read data, centered with write data. for the x16, ldqs corresponds to the data on ldq0 - ldq7; udqs corresponds to the data on udq0-udq7. the data strobes dqs, ldqs, udqs may be used in single ended m ode or paired with the optional complementary signals dqs , ldqs , udqs to provide differential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or disables t he complementary data strobe signals. rdqs, (rdqs ) input/ output read data strobe: for the x8 components a rdqs, rdqs pair can be enabled via the emrs(1) for read timing. rdqs, rdqs is not supported on x4 and x16 components. rdqs, rdqs are edge-aligned with read data. if rdqs, rdqs is enabled, the dm function is disabled on x8 components. odt input on die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is applied to each dq, dqs, dqs and dm signal for x4 and dq, dqs, dqs , rdqs, rdqs and dm for x8 configurations. for x16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal. the odt pin will be ignored if the extended m ode register (emrs(1)) is programmed to disable odt. nc no connect: no internal electric al connection is present v ddq supply dq power supply: 1.8v +/- 0.1v v ssq supply dq ground v ddl supply dll power supply: 1.8v +/- 0.1v v ssdl supply dll ground v dd supply power supply: 1.8v +/- 0.1v v ss supply ground vref supply reference voltage (ba2), (a13~a15) nc no connects: ba2, a13 ~ a15 are additional address pins fo r future generation drams and are not connected on the components describes in this datasheet.
page 10 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 1.6 block diagrams block diagram 16mbit x 4 i/o x 4 internal memory banks, (64 mbit x 4 organisation with 13 row, 2 bank and 11 column external addresses) receivers 2 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 11 command decode a0-a12, ba0, ba1 cke 15 15 i/o gating dm mask logic bank0 memory array (8192 x 512 x 16) sense amplifiers bank1 bank2 bank3 15 9 2 2 2 refresh counter 4 4 4 input register 1 1 1 1 1 16 16 4 16 data mask data ck, col0,1 col0,1 col0,1 mux dqs generator 1 1 4 16 dq0-dq3, dm dqs read latch write fifo & drivers column decoder 512 (x16) row-address mux registers 13 8192 bank0 row-address latch & decoder 8192 address register drivers bank control logic ck 4 4 dqs dqs 1 1 4 4 4 4 4 4 4 4 ap 15 note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional dq and dqs signals.
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 11 rev. 1.02 may 2004 block diagram 8mbit x 8 i/o x 4 internal memory banks (32mb x 8 organisation with 13 row, 2 bank and 10 column external addresses) ras cas ck cs we ck control logic column-address counter/latch mode 10 command decode a0-a12, ba0, ba1 cke 15 i/o gating dm mask logic bank0 memory array (8192x256x32) sense amplifiers bank1 bank2 bank3 15 8 2 2 2 refresh counter 32 col0,1 dq0-dq7, dm dqs column decoder 256 (x32) row-address mux registers 13 8192 bank0 row-address latch & decoder 8192 address register bank control logic 15 receivers 1 dqs ck, ck dll 8 8 8 input register 1 1 1 1 1 32 4 32 data mask data ck, col0,1 col0,1 mux dqs generator 1 1 8 32 read latch write fifo & drivers drivers ck 8 8 dqs 1 1 8 8 8 8 8 8 8 8 dqs ap 15 note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional dq and dqs signals.
page 12 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram block diagram 4mbit x 16 i/o x 4 internal memory banks (16mb x 16 organisation with 13 row, 2 bank and 9 column external addresses) ras cas ck cs we ck control logic column-address counter/latch mode 9 command decode a0-a12, ba0, ba1 cke 15 i/o gating dm mask logic bank0 memory array (8192 x 128 x 64) sense amplifiers bank1 bank2 bank3 15 7 2 2 2 refresh counter 64 col0 ldq0-ldq7 ldm ldqs column decoder 128 (x64) row-address mux registers 13 16384 bank0 row-address latch & decoder 8192 address register bank control logic 15 receivers 1 dqs ck, ck dll 16 16 16 input register 2 2 2 2 2 64 8 64 data mask data ck, col0,1 col0,1 mux dqs generator 2 2 16 64 read latch write fifo & drivers drivers ck 16 16 dqs 2 2 16 16 16 16 16 16 16 16 ldqs udqs udqs ap 15 udq0-udq7 udm note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 13 rev. 1.02 may 2004 2. functional description 2.1 simplified state diagram reading_ap idle mrs t mrd reading refa t rfc bank active t rp t rcd r e a d read_ap writing writing_ap w r i t e write_ap selfrefresh active pd ckeh precharge pd pd_entry ckeh r e f s refsx r e a d _ a p w r i t e _ a p write read autorefreshing setting mrs or emrs precharging activating initialization rl + bl/2 + t rtp sequence act pre wl + bl/2 + wr ckel ckel ckel pd_entry automatic sequence command sequence pre this simplified state diagram is intended to provide a floorplan of the possible state transitions and the commands to control them. in particular situations involving more than one bank, enabling / disabling on-die termination, power-down entry / exit - among other things - are not captured in full detail.
page 14 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.2 basic functionality read and write accesses to the ddr2 sdram are burst oriented; accesses start at a selected location and con- tinue for the burst length of four or eight in a programmed sequence. accesses begin with the registration of an activate command, which is followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed (ba0 & ba1 select the bank, a0-a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto-precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed informa- tion covering device initialization, register definition, command description and device operation. 2.2.1 power on and initialization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. power-up and initialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2 * vddq and odt at a low state (all other inputs may be undefined). to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. maximum power up interval for vdd/vddq is specified as 10.0 ms. the power interval is defined as the amount of time it takes for vdd / vddq to power-up from 0v to 1.8 v +/- 100 mv. - vdd,vddl and vddq are driven from a single power converter output, and - vtt is limited to 0.95 v max, and - vref tracks vddq/2 or - apply vdd before or at the same time as vddl, - apply vddl before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. at least one of these two sets of conditions must be met. 2. start clock (ck, ck ) and maintain stable power and clock condition for a minimum of 200 s. 3. apply nop or deselect commands & take cke high. 4. wait minimum of 400ns, then issue a precharge-all command. 5. issue emrs(2) command. (to issue emrs(2) command, provide ?low? to ba0 and ba2 and ?high? to ba1) 6. issue emrs(3) command. (to issue emrs(3) command, provide ?low? to ba2 and ?high? to ba0 and ba1) 7. issue emrs(1) command to enable dll. (to issue ?dll enable? command, provide ?low? to a0 and ?high? to ba0 and ?low? to ba1,ba2 and a13~a15) 8. issue mrs command (mode register set) for "dll reset". (to issue dll reset command, provide ?high? to a8 and ?low? to ba0 ~ ba2 and a13 ~ a15) 9. issue precharge-all command. 10. issue 2 or more auto-refresh commands. 11. issue a mrs command with low on a8 to initialize device operation. (i.e. to program operating parameters with out resetting the dll) 12. at least 200 clocks after step 8, execute ocd calibration (off chip driver impedance adjustment). if ocd cali- bration is not used, emrs ocd default command (a9=a8=a7=1) followed by emrs(1) ocd calibration mode exit command (a9=a8=a7=0) must be issued with other parameters of emrs(1). 13. the ddr2 sdram is now ready for normal operation.
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 15 rev. 1.02 may 2004 example: 2.2.2 programming the mode register and extended mode registers for application flexibility, burst length, burst type, cas latency, dll reset function, write recovery time (wr) are user defined variables and must be programmed with a mode register set (mrs) command. additionally, dll disable function, additive cas latency, driver impedance, odt (on die termination), single-ended strobe and ocd (off chip driver impedance adjustment) are also user defined variables and must be programmed with an extended mode register set (emrs) command. contents of the mode register (mrs) and extended mode reg- isters (emrs(#)) can be altered by re-executing the mrs and emrs commands. if the user chooses to modify only a subset of the mrs or emrs variables, all variables must be redefined when the mrs or emrs commands are issued. also any programming of emrs(2) or emrs(3) must be followed by programming of mrs and emrs(1). after initial power up, all mrs and emrs commands must be issued before read or write cycles may begin. all banks must be in a precharged state and cke must be high at least one cycles before the mode regis- ter set command can be issued. either mrs or emrs commands are activated by the low signals of cs , ras , cas and we at the positive edge of the clock. when both bank addresses ba0 and ba1 are low, the ddr2 sdram enables the mrs command. when the bank addresses ba0 is high and ba1 low, the ddr2 sdram enables the emrs(1) command. the address input data during this cycle defines the parameters to be set as shown in the mrs and emrs table. a new command may be issued after the mode register set command cycle time (tmrd). mrs, emrs and dll reset do not affect array contents, which means re-initialization including those can be executed any time after power-up without affecting array contents. 2.2.3 ddr2 sdram mode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr2 sdram. it programs c as latency, burst length, burst sequence, test mode, dll reset, wr (write recovery) and various vendor specific options to make ddr2 sdram useful for various applications. the default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. the mode register is written by asserting low on cs , ras , cas , we , ba0 and ba1, while controlling the state of address pins a0 ~ a13. the ddr2 sdram should be in all bank precharge (idle) mode with cke already high prior to writing into the mode register. the mode register set command cycle time (t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. the mode register is divided into various fields depending on functionality. burst length is defined by a0 ~ a2 with options of 4 and 8 bit burst length. burst address sequence type is defined by a3 and c as latency is defined by a4 ~ a6. a7 is used for test mode and must be set to low for normal mrs operation. a8 is used for dll reset. a9 ~ a11 are used for write recovery time (wr) definition for auto-precharge mode. with address bit a12 two power-down modes can be selected, a ?standard mode? and a ?low-power? power-down mode, where the dll is disabled. address bit a13 and all ?higher? address bits (including ba2) have to be set to ?low? for compatibility with other ddr2 memory products with higher memory densities. 1st auto refresh ck, ck mrs pre all emrs(3) trp tmrs tmrs cke 400 ns nop odt "low" emrs(2) tmrs emrs(1) tmrs pre all trp trfc 2nd auto refresh trfc extended mode register(1) set with dll enable mode register set with dll reset min. 200 cycles to lock the dll mrs tmrs follow ocd flowchart emrs(1) ocd emrs(1) ocd any command ocd drive(1) or ocd default ocd calibration mode exit mode register set w/o dll reset tmrs
page 16 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram mrs mode register operation table (address input for mode set) a8 dll reset 0no 1 yes a12 active power-down mode select 0 fast exit (use txard) 1 slow exit (use txards) a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address field bt burst length cas latency mode a6 a5 a4 latency 000 reserved 001 reserved 0102 (optional) ***) 011 3 100 4 101 5 110 reserved 111 reserved burst type 0 sequential 1 interleave ba1 ba0 tm register a7 mode 0normal 1 test dll wr 0* a11 a10 a9 wr **) 0 0 0 reserved 001 2 010 3 011 4 100 5 101 6 1 1 0 reserved 1 1 1 reserved a2 a1 a0 burst length 010 4 011 8 a13~ a12 0* 0* ba1 ba0 mrs mode 00 mrs 01emrs(1) 10 emrs(2): reserved 11 emrs(3): reserved pd ba2 0* a15 *) must be programmed to 0 when setting the mode register. a13 ~ a15 and ba2 are reserved for future use and must be programmed to 0 when setting the mode register mrs **) the programmability of wr (write recovery) is fo r writes with auto-precharge only and defines the time when the device starts prechar ge internally. wr must be programmed to fulfill the minimum retirement for the analogue twr timing. ***) cas latency = 2 is implemented in this desi gn, but functionality is not tested and guaranteed.
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 17 rev. 1.02 may 2004 2.2.4 ddr2 sdram extended mode register set (emrs(1)) the extended mode register emrs(1) stores the data for enabling or disabling the dll, output driver strength, additive latency, ocd program, odt, dqs and output buffers disable, rqds and rdqs enable. the default value of the extended mode register emrs(1) is not defined, therefore the extended mode register must be writ- ten after power-up for proper operation. the extended mode register is written by asserting low on cs , ras , cas , we, ba1 and high on ba0, while controlling the state of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (tmrd) must be satisfied to complete the write operation to the emrs(1). mode register con- tents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. emrs(1) extended mode register operation table (address input for mode set) address field rdqs extended mode register dll 1 d.i.c ba1 ba0 a11 a10a9a8a7a6a5a4a3a2a1a0 additive latency a5 a4 a3 additivelatency 000 0 001 1 010 2 011 3 100 4 101 reserved 110 reserved 111 reserved a9 a8 a7 ocd calibration program 000 ocd cal. mode exit, maintain setting 001 drive (1) 010 drive (0) 100 adjust mode ocd program 0* dqs rtt a10 0enable 1 d isable a0 dll enable 0enable 1 d isable rtt a6 rtt (nom.) 0 odt disabled 1 75 ohm a2 0 0 0 1 1 1 150 ohm reserved dqs,(rdqs) disable a12 a13~a15 0* qoff 11 1 ocd calibration default *) must be programmed to 0 for compatibility with future ddr2 memory products. a11 rdqs,(rqds) enable 0 d isable 1enable a12 qoff 0 1 output buffers enabled output buffers disabled ba2 0* ba0 mrs mode 0mrs 1 emrs(1) ba1 0 0 1 1 1 0 emrs(2) emrs(3) a) b) a) when adjust mode is issued, al from previously set value must be applied b) after setting to default, ocd mode needs to be exited by setting a9~a7 to 000. refer to the following 2.2.2.5 section for detailed information. a) a) disables dq, dqs, dqs, rdqs, rdqs a1 output driver impedence control driver size 0normal 100% 1 weak 60%
page 18 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram a0 is used for dll enable or disable. a1 is used for enabling half-strength data-output driver. a2 and a6 enables odt (on-die termination) and sets the rtt value. a3~a5 are used for additive latency settings and a7 ~ a9 enables the ocd impedance adjustment mode. a10 enables or disables the differential dqs and rdqs signals, a11 disables or enables rdqs. address bit a12 have to be set to ?low? for normal operation. with a12 set to ?high? the sdram outputs are disabled and in hi-z. ?high? on ba0 and ?low? for ba1 have to be set to access the emrs(1). a13 and all ?higher? address bits (including ba2) have to be set to ?low? for compatibility with other ddr2 memory products with higher memory densities. refer to the table for specific codes on the previous page. single-ended and differential data strobe signals the following table lists all possible combinations for dqs, dqs , rdqs, rqds which can be programmed by a10 & a11 address bits in emrs(1). rdqs and rdqs are available in x8 components only. if rdqs is enabled in x8 components, the dm function is disabled. rdqs is active for reads and don?t care for writes: dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self-refresh operation and is automatically re-enabled and reset upon exit of self-refresh operation. any time the dll is reset, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. less clock cycles may result in a violation of the tac or tdqsck parameters. output disable (qoff) under normal operation, the dram outputs are enabled during read operation for driving data (qoff bit in the emrs(1) is set to 0). when the qoff bit is set to 1, the dram outputs will be disabled. disabling the dram out- puts allows users to measure idd currents during read operations, without including the output buffer current. emrs(1) strobe function matrix signaling a11 (rdqs enable) a10 (dqs enable) rdqs/dm rdqs dqs dqs 0 (disable) 0 (enable) dm hi-z dqs dqs differential dqs signals 0 (disable) 1 (disable) dm hi-z dqs hi-z single-ended dqs signals 1 (enable) 0 (enable) rdqs r dqs dqs dqs differential dqs signals 1 (enable) 1 (disable) rdqs hi-z dqs hi-z single-ended dqs signals
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 19 rev. 1.02 may 2004 2.2.5 emrs(2) extended mode register the extended mode registers emrs(2) and emrs(3) are reserved for future use and must be programmed when setting the mode register during initialization. the extended mode register emrs(2) is written by asserting low on cs , ras , cas , we, ba2, ba0 and high on ba1, while controlling the state of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (tmrd) must be satisfied to complete the write operation to the emrs(2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state 2.2.6 emrs(3) extended mode register the extended mode register emrs(3) is reserved for future use and all bits except ba0 and ba1 must be pro- grammed to 0 when setting the mode register during initialization . address field extended mode register(2) ba1 ba0 a11 a10a9a8a7a6a5a4a3a2a1a0 0 a12 a13~a15 ba2 0* 1 0* emrs(2) *) must be programmed to "0" address field extended mode register(3) ba1 ba0 a11 a10a9a8a7a6a5a4a3a2a1a0 1 a12 a13~a15 ba2 0* 1 0* *) must be programmed to "0"
page 20 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.3 off-chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart below is an example of the sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd impedance adjustment and odt (on die termination) should be carefully controlled depending on system environment. start emrs: drive (1) dq & dqs high; dqs low test emrs : enter adjus t mode bl=4 cod e inpu t to all dqs inc, dec, or nop emrs: drive(0) dq & dqs low; dqs high test emrs : enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit end all ok all ok need calibration emrs: ocd calibration mode exit mrs should be set before entering ocd impedance adjustment and odt should be carefully controlled depending on system environment emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit emrs: ocd calibration mode exit need calibration
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 21 rev. 1.02 may 2004 extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs(1) mode. in drive mode all outputs are driven out by ddr2 sdram and drive of rdqs is dependent on emrs(1) bit enabling rdqs operation. in drive(1) mode, all dq, dqs (and rdqs) signals are driven high and all dqs (and rdqs) signals are driven low. in drive(0) mode, all dq, dqs (and rdqs) signals are driven low and all dqs (and rdqs) signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characteristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. output driver characteristics for ocd calibration default are specified in the following table. ocd applies only to normal full strength output drive setting defined by emrs(1) and if half strength is set, ocd default driver charac- teristics are not applicable. when ocd calibration adjust mode is used, ocd default output driver characteristics are not applicable. after ocd calibration is completed or driver strength is set to default, subsequent emrs(1) commands not intended to adjust ocd characteristics must specify a7~a9 as?000? in order to maintain the default or calibrated value. off- chip-driver program ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs(1) command along with a 4 bit burst code to ddr2 sdram as in the following table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive the burst code to all dqs at the same time. dt0 in the table means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the driver output impedance is adjusted for all ddr2 sdram dqs simultaneously and after ocd calibration, all dqs of a given ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step within the maxi- mum step count range. when adjust mode command is issued, al from previously set value must be applied. off- chip-driver adjust program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs, (rdqs) high and dqs , (rdqs ) low 0 1 0 drive(0) dq, dqs, (rdqs) low and dqs , (rdqs ) high 1 0 0 adjust mode 1 1 1 ocd calibration default 4 bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull-up driver strength pull-down driver strength 00 0 0 nop (no operation) nop (no operation) 00 0 1 increase by 1 step nop 00 1 0 decrease by 1 step nop 01 0 0 nop increase by 1 step 10 0 0 nop decrease by 1 step 01 0 1 increase by 1 step increase by 1 step 01 1 0 decrease by 1 step increase by 1 step 10 0 1 increase by 1 step decrease by 1 step 10 1 0 decrease by 1 step decrease by 1 step other combinations reserved reserved
page 22 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram for proper operation of adjust mode, wl = rl - 1 = al + cl -1 clocks and tds / tdh should be met as the follow- ing timing diagram. input data pattern for adjustment, dt0 - dt3 is fixed and not affected by mrs addressing mode (i.e. sequential or interleave). burst length of 4 have to be programmed in the mrs for ocd impedance adjustment. drive mode drive mode, both drive(1) and driv e(0), is used for controllers to measure ddr2 sdram driver impedance before ocd impedance adjustment. in this mode, all outputs are driven out toit after ?enter drive mode? com- mand and all output drivers are turned-off toit after ?ocd calibration mode exit? command as the following timing diagram. nop nop nop nop nop em r s(1) cmd dq_in nop tw r dqs_in ck, ck wl em r s(1) nop dm dqs ocd adjust mode ocd calibration mode exit tds tdh dt0 dt1 dt2 dt3 nop nop nop nop e m r s (1) cmd dq_in nop dqs_in ck, ck e m r s (1) enter drive mode ocd calibration mode exit nop dqs high & dqs low for drive(1), dqs low & dqs high for drive 0 dqs high for drive(0) dqs high for drive(1) toit toit
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 23 rev. 1.02 may 2004 2.4 on-die termination (odt) odt (on-die termination) is a new feature on ddr2 comp onents that allows a dram to turn on/off termination resistance for each dq, dqs, dqs and dm for x4 and dq, dq?s dm, rdqs (dm and rdqs share the same pin), and r dqs for x8 configuration via the odt control pin, where d qs is terminated only when enabled in the emrs(1) by address bit a10 = 0. for x8 configuration rdqs is only terminated, when enabled in the emrs(1) by address bits a10 = 0 and a11 = 1. for x16 configuration odt is applied to each udq, ldq, udqs, udqs , ldqs, ldqs , udm and ldm signal via the odt control pin, where udqs and ldqs are terminated only when enabled in the emrs(1) by address bit a10 = 0. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. the odt function can be used for all active and standby modes. odt is turned off and not supported in self- refresh mode. functional representation of odt switch sw1 or sw2 is enabled by the odt pin. selection between sw1 or sw2 is determined by ?rtt (nominal)? in emrs(1) address bits a6 & a2. target rtt = 0.5 * rval1 or 0.5 * rval2 . the odt pin will be ignored if the extended mode register (emrs(1)) is programmed to disable odt. dram input buffer input pin rval1 rval1 rval2 rval2 sw1 sw1 sw2 sw2 vddq vddq vssq vssq
page 24 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram odt truth tables the odt truth table shows which of the input pins are terminated depending on the state of address bit a10 and a11 in the emrs(1) for all three device organisations (x4, x8 and x16). to activate termination of any of these pins, the odt function has to be enabled in the emrs(1) by address bits a6 and a2. odt timing modes depending on the operating mode synchronous or asynchronous odt timings apply. synchronous timings (taond, taofd, taon and taof) apply for all modes, when the on-die dll is not disabled. these modes are: active mode standby mode fast exit active power down mode (with mrs bit a12 is set to ?0?) asynchronous odt timings (taofpd, taonpd) apply when the on-die dll is disabled. these modes are: slow exit active power down mode (with mrs bit a12 is set to ?1?) precharge power down mode input pin emrs(1) address bit a10 emrs(1) address bit a11 x4 components: dq0~dq3 x x dqs x x dqs 0 x dm x x x8 components: dq0~dq7 x x dqs x x dqs 0 x rdqs x 1 rdqs 0 1 dm x 0 x16 components: ldq0~ldq7 x x udq0~udq7 x x ldqs x x ldqs 0 x udqs x x udqs 0 x ldm x x udm x x x = don?t care; 0 = bit set to low; 1 = bit set to high
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 25 rev. 1.02 may 2004 odt timing for active and standby (idle) modes (synchronous odt timings) odt timing for precharge power-down and active power-down mode (with slow exit) (asynchronous odt timings) 1) synchronous odt timings apply for active mode and standby m ode with cke ?high? and for the ?fast exit? active power down mode (mrs bit a12 set to ?0?). in all these modes the on-die dll is enabled. 2) odt turn-on time (t aon,min ) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max. (t aon,max ) is when the odt resistance is fully on. both are measured from t aond. 3) odt turn off time min. (t aof,min ) is when the device starts to turn off the odt resistance.odt turn off time max. (t aof,max ) is when the bus is in high impedanc e. both are measured from t aofd. cke dq odt01 odt ck, ck see note 1 rtt taon(min) taon(max) taof(max) taof(min) taond (2 tck) taofd (2.5 tck) t is t is t0 t1 t2 t3 t4 t5 t6 t7 t8 1) asynchronous odt timings apply for precharge power-down mode and ?slow exit? active power down mode (mrs bit a12 set to ?1?), where the on-die dll is dis abled in this mode of operation. taofpd,min cke dq odt odt02 ck, ck "low" t0 t1 t2 t3 t4 t5 t6 t7 t8 t is t is rtt taonpd,min taofpd,max taonpd,max
page 26 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram odt timing mode switch when entering the power down modes ?slow exit? active power down and precharge power down two addi- tional timing parameters (tanpd and taxpd) define if synchronous or asynchronous odt timings have to be applied. mode entry: as long as the timing parameter tanpdmin is satisfied when odt is turned on or off before entering these power- down modes, synchronous timing parameters can be applied. if tanpdmin is not satisfied, asynchronous timing parameters apply cke ck, ck tanpd (3 tck) t0 t1 t2 t-1 t-2 t-3 t-4 t-5 t is odt03 odt turn-off, tanpd >= 3 tck : odt turn-off, tanpd <3 tck : taofd rtt odt t is rtt t is odt taond rtt taonpdmax odt odt turn-on, tanpd >= 3 tck : synchronous timings apply synchronous timings apply asynchronous timings apply taofpdmax odt rtt asynchronous timings apply odt turn-on, tanpd < 3 tck : t is
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 27 rev. 1.02 may 2004 mode exit: as long as the timing parameter taxpdmin is satisfied when odt is turned on or off after exiting these power- down modes, synchronous timing parameters can be applied. if taxpdmin is not satisfied, asynchronous timing parameters apply cke taxpd odt04 odt turn-off, taxpd >= taxpdmin: rtt rtt taonpdmax t0 t1 t5 t6 t7 t8 t is synchronous timings apply t9 odt turn-off, taxpd < taxpdmin: asynchronous timings apply odt taofd rtt odt taofpdmax rtt odt turn-on, taxpd >= taxpdmin: synchronous timings apply taond t is t is odt t is odt t is odt turn-on, taxpd < taxpdmin: asynchronous timings apply t10 ck, ck
page 28 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.5 bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank addresses ba0 and ba1 are used to select the desired bank. the row addresses a0 through a12 are used to determine which row to activate in the selected bank for x4 and x8 organised components. for x16 components row addresses a0 through a12 have to be applied. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command (with or without auto-precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the trcdmin specification, then additive latency must be programmed into the device to delay the r/w command which is internally issued to the device. the additive latency value must be chosen to assure trcdmin is satisfied. additive latencies of 0, 1, 2, 3 and 4 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as tras and trp, respectively. the minimum time interval between successive bank activate commands to the same bank is determined (trc). the minimum time interval between bank active commands, to any other bank, is the bank a to bank b delay time (trrd). bank activate command cycle: trcd = 3, al = 2, trp = 3, trrd = 2 address nop command t0 t2 t1 t3 t4 col. addr. bank a row addr. bank b col. addr. bank b internal ras-cas delay trcdmin. bank a to bank b delay trrd. activate bank b read a posted cas activate bank a read b posted cas read a begins row addr. bank a addr. bank a precharge bank a nop addr. bank b precharge bank b row addr. bank a activate bank a trp row precharge time (bank a) trc row cycle time (bank a) tn tn+1 tn+2 tn+3 act tras row active time (bank a) additive latency al=2 ck, ck tccd
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 29 rev. 1.02 may 2004 2.6 read and write comm ands and ac cess modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. w e must also be defined at this time to determine whether the access cycle is a read operation (we high) or a write operation (we low). the ddr2 sdram provides a wide variety of fast access modes. a single read or write command will initiate a serial read or write operation on successive clock cycles at data rates of up to 667mb/sec/pin for main memory. the boundary of the burst cycle is restricted to specific segments of the page length. for example, the 16mbit x 4 i/o x 4 bank chip has a page length of 2048 bits (defined by ca0-ca9 & ca11). in case of a 4-bit burst operation (burst length = 4) the page length of 2048 is divided into 512 uniquely address- able segments (4-bits x 4 i/o each). the 4-bit burst operation will occur entirely within one of the 512 segments (defined by ca0-ca8) beginning with the column address supplied to the device during the read or write com- mand (ca0-ca9 & a11). the second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence. in case of a 8-bit burst operation (burst length = 8) the page length of 2048 is divided into 256 uniquely address- able double segments (8-bits x 4 i/o each). the 8-bit burst operation will occur entirely within one of the 256 dou- ble segments (defined by ca0-ca7) beginning with the column address supplied to the device during the read or write command (ca0-ca9 & ca11). a new burst access must not interrupt the previous 4 bit burst operation in case of bl = 4 setting. therefore the minimum cas to cas delay (tccd) is a minimum of 2 clocks for read or write cycles . for 8 bit burst operation (bl = 8) the minimum c as to cas delay (tccd) is 4 clocks for read or write cycles. burst interruption is allowed with 8 bit burst operation. for details see the ?burst interrupt? - section of this datasheet. example: read burst timing example: (cl = 3, al = 0, rl = 3, bl = 4) nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t12 cmd dq rb dq s, dq s read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout c0 dout c1 dout c2 dout c3 no p read c tccd tccd ck, ck
page 30 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.6.1 posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a read or write command to be issued immediately after the ras bank activate command (or any time during the ras to cas delay time, trcd, period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is the sum of al and the cas latency (cl). therefore if a user chooses to issue a read/write command before the trcdmin, then al greater than 0 must be written into the emrs(1). the write latency (wl) is always defined as rl - 1 (read latency -1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). if a user chooses to issue a read command after the trcdmin period, the read latency is also defined as rl = al + cl. examples: read followed by a write to the same bank, activate to read delay < trcdmin: al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 4 read followed by a write to the same bank, activate to read delay < trcdmin: al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 8 activate bank a trcd cl = 3 al = 2 rl = al + cl = 5 wl = rl -1 = 4 postcas1 cmd dq dqs, dqs ck, ck 0 2 34 5 1 67891011 dout0 dout1 dout2 dout3 din0 din1 din2 din3 bank a read write bank a activate bank a trcd cl = 3 al = 2 rl = al + cl = 5 wl = rl -1 = 4 postcas3 cmd dq dqs, dqs ck, ck 0 2 34 5 1 67891011 bank a read write bank a din0 din1 din2 din3 dout0 dout1 dout2 dout3 dout4 dout5 dout6 dout7 12
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 31 rev. 1.02 may 2004 read followed by a write to the same bank, activate to read delay = trcdmin: al = 0, cl = 3, rl = (al + cl) = 3, wl = (rl -1) = 2, bl = 4 read followed by a write to the same bank, activate to read delay > trcdmin: al = 1, cl = 3, rl = 4, wl = 3, bl = 4 activate bank a bank a write trcd cl = 3 al = 0 rl = al + cl = 3 wl = rl -1 = 2 postcas2 bank a cmd dq dqs, dqs ck, ck 0 2 34 5 1 67891011 read dout0 dout1 dout2 dout3 din0 din1 din2 din3 activate bank a trcd > trcdmin. rl = 4 wl = 3 postcas5 cmd dq dqs, dqs ck, ck 0 2 34 5 1 67891011 bank a read dout0 dout1 dout2 dout3 din0 din1 din2 din3 write bank a 12 1 3
page 32 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.6.2 burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a0 ~ a2 of the mrs. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mrs. seamless burst read or write operations are supported. interruption of a burst read or write operation is prohibited, when burst length = 4 is pro- grammed. for burst interruption of a read or write burst when burst length = 8 is used, see the ?burst interruption ?section of this datasheet. a burst stop command is not supported on ddr2 sdram devices. burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 notes: 1) page size for all 256mbit components is 1 kbyte 2) order of burst access for sequential addressing is ?nibble-based? and therefore different from sdr or ddr components
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 33 rev. 1.02 may 2004 2.6.3 burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register set (emrs(1)). examples: basic burst read timing burst read operation: rl = 5 (al = 2, cl = 3, bl = 4) dqs, dqs dq dqs dqs t rpre t dqsqmax t rpst t dqsck t ac dout dout dout dout clk, clk clk clk t ch t cl t ck do-read t qh dqsqmax t qh t t lz t hz nop nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop <= tdqsck cmd dq bread523 dq s, dq s post cas ck, ck
page 34 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram the minimum time from the burst read command to the burst write command is defined by a read-to-write turn- around time, which is bl/2 + 2 clocks. burst read operation: rl = 3 (al = 0, cl = 3, bl = 8) burst read followed by burst write: rl = 5, wl = (rl-1) = 4, bl = 4 cmd nop nop nop nop nop nop dq's nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 3 cl = 3 nop <= tdqsck bread303 dq s, dq s dout a4 dout a5 dout a6 dout a7 ck, ck nop posted cas write a nop nop nop nop nop read a posted cas t0 t1 dout a0 dout a1 dout a2 dout a3 rl = 5 nop cmd dq brbw514 t3 t4 t5 t6 t7 t8 t9 din a0 din a1 din a2 din a3 dq s, dq s wl = rl - 1 = 4 bl/2 + 2 ck, ck
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 35 rev. 1.02 may 2004 the seamless burst read operation is supported by enabling a read command at every bl / 2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. the seamless, non interrupting 8-bit burst read operation is supported by enabling a read command at every bl / 2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are acti- vated. seamless burst read operation: rl = 5, al = 2, cl = 3, bl = 4 seamless burst read operation: rl = 3, al = 0, cl = 3, bl = 8 (non interrupting) nop nop nop nop nop nop nop read a post cas read b post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 rl = 5 al = 2 cl = 3 sbr523 cmd dq dq s, dq s ck, ck nop nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout a4 dout a5 dout a4 dout a7 rl = 3 cl = 3 sbr_bl8 cmd dq dqs, dqs read b post cas dout b0 dout b1 dout b2 dout b3 do u nop nop nop nop no t9 ck, ck
page 36 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.6.4 burst write command the burst write command is initiated by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl -1). a data strobe signal (dqs) has to be driven low (preamble) a time twpre prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the tdqss specification must be satisfied for write cycles. the subse- quent burst bit data are issued on successive edges of the dqs until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank precharge is named ?write recovery time? (twr) and is the time needed to store the write data into the memory array. twr is an analog timing parameter (see the ac table in this specification) and is not the programmed value for wr in the mrs. example: . basic burst write timing burst write operation: rl = 5 (al = 2, cl = 3), wl = 4, bl = 4 dq s, dq s dq s dq s t dqsh t dqsl t wpre wpst t din din din din t ds t dh nop nop nop nop nop precharge nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 4 bw543 cmd dq nop din a0 din a1 din a2 din a3 <= tdqss tw r completion of the burst write dq s, dq s ck, ck
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 37 rev. 1.02 may 2004 the minimum number of clocks from the burst write command to the burst read command is (cl - 1) +bl/2 + twtr where twtr is the write-to-read turn-around time twtr expressed in clock cycles. the twtr is not a write recov- ery time (twr) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. burst write operation: rl = 3 (al = 0, cl = 3), wl = 2, bl = 4 burst write followed by burst read: rl = 5 (al = 2, cl = 3), wl = 4, twitter = 2, bl = 4 nop nop nop nop nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 2 bw322 cmd dq nop din a0 din a1 din a2 din a3 tw r completion of the burst write <= tdqss precharge bank a activate tr p dq s, dq s ck, ck nop nop nop nop nop read a post cas bwbr cmd dq nop din a0 din a1 din a2 din a3 al=2 cl=3 nop nop tw tr t0 t2 t1 t3 t4 t5 t6 t7 t8 t9 w rite to read = (cl - 1)+ bl/2 +tw tr(2) = 6 dq s, dq s w l = rl - 1 = 4 rl=5 ck, ck
page 38 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram the seamless burst write operation is supported by enabling a write command every bl / 2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. the seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every bl / 2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are acti- vated. seamless burst write operation: rl = 5, wl = 4, bl = 4 seamless burst write operation: rl = 3, wl = 2, bl = 8, non interrupting nop nop nop nop nop nop nop din a0 din a1 din a2 din a3 write a post cas wl = rl - 1 = 4 write b post cas din b0 din b1 din b2 din b3 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbr dq s, dq s ck, ck nop nop nop nop nop nop nop write a wl = rl - 1 = 2 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbw_bl8 dq s, dq s write b din a0 din a1 din a2 din a3 din a4 din a5 din a5 din a7 din b0 din b1 din b2 din b3 din b4 din b5 di n ck, ck
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 39 rev. 1.02 may 2004 2.6.5 write data mask one write data mask input (dm) for x4 and x8 components and two write data mask inputs (ldm, udm) for x16 components are supported on ddr2 sdram?s, consistent with the implementation on ddr sdram?s. it has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. data mask is not used during read cycles. if dm is high during a write burst coincident with the write data, th e write data bit is not written to the memory. for x8 com- ponents the dm function is disabled, when rdqs / rdqs are enabled by emrs(1). . . write data mask timing burst write operation with data mask: rl = 3 (al = 0, cl = 3), wl = 2, twr = 3, bl = 4 dq s, dq s dq s dq s t dqsh t dqsl t wpre wpst t dq din din din din t ds dh t dm don't care nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 2 dm cmd dq nop tw r <= tdqss precharge bank a activate tr p dq s, dq s dm din a0 din a1 din a3 din a2 ck, ck
page 40 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.6.6 burst interruption interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. a read burst of 8 can only be interrupted by another read command. read burst interruption by a write or precharge command is prohibited. 2. a write burst of 8 can only be interrupted by another write command. write burst interruption by a read or precharge command is prohibited. 3. read burst interrupt must occur exactly two clocks after the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt must occur exactly two clocks after the previous write command. any other read burst interrupt timings are prohibited. 5. read or write burst interruption is allowed to any bank inside the ddr2 sdram. 6. read or write burst with auto-precharge enabled is not allowed to be interrupted. 7. read burst interruption is allowed by a read with auto-precharge command. 8. write burst interruption is allowed by a write with auto-precharge command. 9. all command timings are referenced to burst length set in the mode register. they are not referenced to the actual burst. fo r example, minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). minimum write to precharge timing is wl + bl/ 2 + twr, where twr starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. examples: read burst interrupt timing example: (cl = 3, al = 0, rl = 3, bl = 8) nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq rbi dq s, dq s read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout b4 dout b5 dout b6 dout b ck, ck
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 41 rev. 1.02 may 2004 write burst interrupt timing example: (cl = 3, al = 0, wl = 2, bl = 8) nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq wbi dq s, dq s nop din a0 din a1 din a2 din a3 din b0 din b1 din b2 din b3 dout b4 din b5 din b6 din b7 write b ck, ck nop
page 42 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.7 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when cs , ras and we are low and cas is high at the rising edge of the clock. the pre- charge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba0 and ba1 are used to define which bank to precharge when the command is issued. bank selection for precharge by address bits note: the bank address assignment is the same for activating and precharging a specific bank. 2.7.1 burst read operation followed by a precharge the following rules apply as long as the trtp timing parameter - internal read to precharge command delay time - is less or equal two clocks, which is the case for ope rating frequencies less or equal 266 mhz (ddr2 400 and 533 speed sorts): minimum read to precharge command spacing to the same bank = al + bl/2 clocks. for the earliest possible precharge, the precharge command may be issued on the rising edge which is ?additive latency (al) + bl/2 clocks? after a read command, as long as the minimum tras timing is satisfied. a new bank active command may be issued to the same bank if the following two conditions are satisfied simulta- neously: (1) the ras precharge time (trp) has been satisfied from the clock at which the precharge begins. (2) the ras cycle time (trcmin) from the previous bank activation has been satisfied. for operating frequencies higher than 266 mhz, trtp becomes > 2 clocks and one additional clock cycle has to be added for the minimum read to precharge command spacing, which now becomes al + bl/2 + 1 clocks. a10 ba0 ba1 precharge bank(s) low low low bank 0 only low low high bank 1 only low high low bank 2 only low high high bank 3 only high don?t care don?t care all banks
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 43 rev. 1.02 may 2004 examples: burst read operation followed by precharge: rl = 4 (al = 1, cl = 3), bl = 4, trtp <= 2 clocks burst read operation followed by precharge: rl = 4 (al = 1, cl = 3), bl = 8, trtp <= 2 clocks nop precharge nop bank a a ctivate nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 tr p dq s, dq s nop >=trc >=trtp ck, ck nop nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p413(8) nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 tr p dq s, dq s nop >=trc >=trtp dout a4 dout a5 dout a6 dout a7 precharge nop bank a a ctivate first 4-bit prefetch second 4-bit prefetch ck, ck
page 44 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram burst read operation followed by precharge: rl = 5 (al = 2, cl = 3), bl = 4, trtp <= 2 clocks burst read operation followed by precharge: rl = 6, (al = 2, cl = 4), bl = 4, trtp <= 2 clocks nop nop nop bank a a ctivate nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p523 nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 3 rl = 5 >=tras cl = 3 tr p precharge dq s, dq s >=trc >=trtp ck, ck nop nop nop read a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p624 nop al + bl/2 clocks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 4 rl = 6 >=tras cl = 4 tr p precharge a bank a a ctivate dq s, dq s nop nop >=trc >=trtp ck, ck
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 45 rev. 1.02 may 2004 burst read operation followed by precharge: rl = 4, (al = 0, cl = 4), bl = 8, trtp > 2 clocks nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p404(8) nop a l + b l/2 clks + 1 dout a0 dout a1 dout a2 dout a3 cl = 4 rl = 4 >=tras tr p dq s, dq s nop >=trtp dout a4 dout a5 dout a6 dout a7 precharge nop bank a a ctivate first 4-bit prefetch second 4-bit prefetch ck, ck
page 46 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.7.2 burst write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + twr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time (t wr) referenced from the completion of the burst write to the pre- charge command. no precharge command should be issued prior to the twr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. twr is an analog timing parameter (see the ac table in this datasheet) and is not the programmed value for twr in the mrs. examples: . burst write followed by precharge: wl = (rl - 1) = 3, bl = 4, twr = 3 burst write followed by precharge: wl = (rl - 1) = 4, bl = 4, twr = 3 nop nop nop nop nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 wl = 3 bw-p3 cmd dq nop din a0 din a1 din a2 din a3 tw r completion of the burst write precharge a nop dq s, dq s ck, ck nop nop nop nop nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = 4 bw-p4 cmd dq nop din a0 din a1 din a2 din a3 tw r completion of the burst write precharge a nop dq s, dq s ck, ck
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 47 rev. 1.02 may 2004 2.8 auto-precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the pre- charge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automati- cally begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto-precharge function is enabled. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to precharge internally on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto-precharge is also implemented for write commands.the pre- charge operation engaged by the auto-precharge command will not begin until the last data of the write burst sequence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for random data access. the ras lockout circuit internally delays the precharge operation until the array restore operation has been completed so that the auto-precharge command may be issued with any read or write com- mand. 2.8.1 burst read with auto-precharge if a10 is high when a read command is issued, the read with auto-precharge function is engaged. the ddr2 sdram starts an auto-precharge operation on the rising edge which is (al + bl/2) cycles later from the read with ap command if trasmin and trtp are satisfied. if trasmin is not satisfied at the edge, the start point of auto-precharge operation will be delayed until trasmin is satisfied. if trtpmin is not satisfied at the edge, the start point of auto-precharge operation will be delayed until trtpmin is satisfied. in case the internal precharge is pushed out by trtp, trp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto-precharge to the next activate command becomes al + trtp + trp. for bl = 8 the time from read with auto-precharge to the next activate command is al + 2 + trtp + trp. note that (trtp + trp) has to be rounded up to the next inte- ger value. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simul- taneously: (1) the ras precharge time (trp) has been satisfied from the clock at which the auto-precharge begins. (2) the ras cycle time (trc) from the previous bank activation has been satisfied.
page 48 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram examples: burst read with auto-precharge followed by an activation to the same bank (trc limit) rl = 5 (al = 2, cl = 3), bl = 4, trtp <= 2 clocks burst read with auto-precharge followed by an activation to the same bank (tras limit): rl = 5 (al = 2, cl = 3), bl = 4, trtp <= 2 clocks nop nop nop nop bank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5231 a10 ="high" trp auto-precharge begins dq s, dq s tras trcmin. nop al + bl/2 ck, ck nop nop nop nop bank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5232 a10 ="high" trp auto-precharge begins dq s, dq s trc tras(min) nop ck, ck
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 49 rev. 1.02 may 2004 burst read with auto-precharge followed by an activation to the same bank: rl = 4 (al = 1, cl = 3), bl = 8, trtp <= 2 clocks burst read with auto-precharge followed by an activation to the same bank: rl = 4 (al = 1, cl = 3), bl = 4, trtp > 2 clocks nop nop nop nop bank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap413(8)2 a10 ="high" trp auto-precharge begins dq s, dq s nop dout a4 dout a5 dout a6 dout a7 first 4-bit prefetch second 4-bit prefetch >= trtp al + bl/2 ck, ck nop nop nop nop bank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap4133 a10 ="high" auto-precharge begins dq s, dq s nop first 4-bit prefetch trtp al + trtp + trp trp ck, ck
page 50 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.8.2 burst write with auto-precharge if a10 is high when a write command is issued, the write with auto-precharge function is engaged. the ddr2 sdram automatically begins precharge operation after the completion of the write burst plus the write recovery time delay (wr), programmed in the mrs register, as long as tras is satisfied. the bank undergoing auto-pre- charge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) the last data-in to bank activate delay time (tdal = wr + trp) has been satisfied. (2) the ras cycle time (trc) from the previous bank activation has been satisfied. in ddr2 sdram?s the write recovery time delay (wr) ha s to be programmed into the mrs mode register. as long as the analog twr timing parameter is not violated, wr can be programmed between 2 and 6 clock cycles. minimum write to activate command spacing to the same bank = wl + bl/2 + tdal. examples: burst write with auto-precharge (trc limit): wl = 2, tdal = 6 (wr = 3, trp = 3), bl = 4 nop nop nop nop nop bank a a ctivate nop write w/ap t0 t2 t1 t3 t4 t5 t6 t7 nop cmd dq bw-ap223 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 2 wr trcmin. dq s, dq s completion of the burst write tdal >=trasmin. ck, ck
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 51 rev. 1.02 may 2004 2.8.3 read or write to precharge command spacing summary the following table summarizes the minimum command delays between read, read w/ap, write, write w/ap to the precharge commands to the same banks and precharge-all commands. burst write with auto-precharge (wr + trp limit): wl = 4, tdal = 6 (wr = 3, trp = 3), bl = 4 from command to comm and minimum delay between ?from command? to ?to command? units notes read precharge (to same banks as read) al + bl/2 + max(trtp, 2) - 2*tck tck 1, 2 precharge-all al + bl/2 + max(trtp, 2) - 2*tck tck 1, 2 read w/ap precharge (to same banks as read w/ap) al + bl/2 + max(trtp, 2) - 2*tck tck 1, 2 precharge-all al + bl/2 + max(trtp, 2) - 2*tck tck 1, 2 write precharge (to same banks as write) wl + bl/2 + twr tck 2 precharge-all wl + bl/2 + twr tck 2 write w/ap precharge (to same banks as write w/ap) wl + bl/2 + wr tck 2 precharge-all wl + bl/2 + wr tck 2 precharge precharge (to same banks as precharge) 1*tck tck 2 precharge-all 1*tck tck 2 precharge-all precharge 1*tck tck 2 precharge-all 1*tck tck 2 note 1: rtp[cycles] = ru{trtp(ns) / tck(ns)}, where ru stands for round up. note 2: for a given bank, the precharge period should be counted fr om the latest precharge command, either one bank precharge o r precharge-all, issued to that bank. the pr echarge period is satisfied after trp or trpall depending on the latest prechargte co m- mand issued to that bank nop nop nop nop nop bank a a ctivate nop write w/ap posted cas t0 t3 t4 t5 t6 t7 t12 nop cmd dq bw-ap423 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 4 wr >=trc t9 t8 completion of the burst write dq s, dq s tdal >=tras ck, ck
page 52 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.8.4 concurrent auto-precharge ddr2 devices support the ?concurrent auto-precharge? feature. a read with auto-precharge enabled, or a write with auto-precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between read data and write data must be avoided externally and on the internal data bus. the minimum delay from a read or write command with auto-precharge enabled, to a command to a different bank, is summarized in the table below. as defined, the wl = rl - 1 for ddr2 devices which allows the command gap and corresponding data gaps to be minimized. from command to command (different bank, non-interrupting command) minimum delay with concurrent auto-pre- charge support units note write w/ap read or read w/ap (cl -1) + (bl/2) + twtr tck write or write w/ap bl/2 tck precharge or activate 1 tck 1) read w/ap read or read w/ap bl/2 tck write or write w/ap bl/2 + 2 tck precharge or activate 1 tck 1) note: 1) this rule only applies to a selective prechar ge command to another banks, a precharge-all command is illegal
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 53 rev. 1.02 may 2004 2.9 refresh ddr2 sdram requires a refresh of all rows in any rolling 64 ms interval. the necessary refresh can be generated in one of two ways: by explicit auto-refresh commands or by an internally timed self-refresh mode. 2.9.1 auto-refresh command auto-refresh is used during normal operation of the ddr2 sdram?s. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits?don?t care? during an auto-refresh command. the ddr2 sdram requires auto- refresh cycles at an average periodic interval of trefi (maximum). when cs , ras and cas are held low and we high at the rising edge of the clock, the chip enters the auto- refresh mode. all banks of the sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the auto-refresh command can be applied. an internal address counter supplies the addresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the auto-refresh command and the next activate command or subsequent auto-refresh command must be greater than or equal to the auto-refresh cycle time (t rfc ). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 * trefi. t0 t2 t1 t3 ar ck, ck cmd precharge > = t rp nop a u to refresh any nop > = t rfc > = t rfc a u t o refresh nop nop nop cke "high"
page 54 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.9.2 self-refresh command the self-refresh command can be used to retain data, even if the rest of the system is powered down. when in the self-refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built-in timer to accommodate self-refresh operation. the self-refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs(1) command. once the command is regis- tered, cke must be held low to keep the device in self-refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self-refresh mode all of the external control signals, except cke, are ?don?t care?. the dram initiates a minimum of one auto refresh command internally within tcke period once it enters self refresh mode. the clock is internally disabled during self-refresh operation to save power. the minimum time that the ddr2 sdram must remain in self refresh mode is tcke. the user may change the external clock frequency or halt the external clock one clock after self-refresh entry is registered, however, the clock must be restarted and stable before the device can exit self-refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back high. once self-refresh exit command is registered, a delay of at least txsnr must be satis- fied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self-refresh exit period txsrd for proper operation. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after txsnr expires. nop or deselect commands must be registered on each positive clock edge during the self-refresh exit interval txsnr. odt should be turned off dur- ing txsrd. the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, the ddr2 sdram requires a mini- mum of one extra auto refresh command before it is put back into self refresh mode. * = device must be in the ?all banks idle? state before entering self refresh mode. txsrd (>=200 tck) has to be satisfied for a read or a read with auto-precharge command. txsnr has to be satisfied for any command except a read or a read with auto-precharge command since cke is an sstl input, vref must be maintained during self refresh. ck/ck t1 t3 t2 ck/ck may be halted ck/ck must be stable cke >=txsrd >= txsnr tn tr tm t5 t4 trp* tis taofd cmd self refresh e ntry nop non-read command r ead command t0 tis tis odt tcke
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 55 rev. 1.02 may 2004 2.10 power-down power-down is synchronously entered when cke is registered low, along with nop or deselect command. cke is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. cke is allowed to go low while any other operation such as row activation, precharge, auto-pre- charge or auto-refresh is in progress, but power-down idd specification will not be applied until finishing those operations. the dll should be in a locked state when power-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation. dram design guarantees it?s dll in a locked state with any cke intensive operations as long as dram controller complies with dram specifications. if power-down occurs when all banks are precharged, this mode is referred to as precharge power-down ; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down . for active power-down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to ?low? this mode is referred as ?standard active power-down mode? and a fast power-down exit timing defined by the txard timing parameter can be used. when a12 is set to ?high? this mode is referred as a power saving ?low power active power-down mode?. this mode takes longer to exit from the power-down mode and the txards timing parameter has to be satisfied. entering power-down deactivates the input and output buffers, excluding ck, ck , odt and cke. also the dll is disabled upon entering precharge power-down or slow exit active power-down, but the dll is kept enabled dur- ing fast exit active power-down. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are ?don?t care?. power-down duration is limited by 9 times trefi of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect com- mand). a valid, executable command can be applied with power-down exit latency, txp, txard or txards, after cke goes high. power-down exit latencies are defined in the ac spec table of this data sheet. power-down entry active power-down mode can be entered after an activate command. precharge power-down mode can be entered after a precharge, precharge-all or internal precharge command. it is also allowed to enter power-mode after an auto-refresh command or mrs / emrs(1) command when tmrd is satisfied. active power-down mode entry is prohibited as long as a read burst is in progress, meaning cke should be kept high until the burst operation is finished. therefore active power-down mode entry after a read or read with auto-precharge command is allowed after rl + bl/2 is satisfied. active power-down mode entry is prohibited as long as a write burst and the internal write recovery is in progress. in case of a write command, active power-down mode entry is allowed when wl + bl/2 + twtr is satisfied. in case of a write command with auto-precharge, power-down mode entry is allowed after the internal precharge command has been executed, which is wl + bl/2 + wr starting from the write with auto-precharge command. in case the ddr2 sdram enters the precharge power-down mode .
page 56 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram examples: active power-down mode entry and exit after an activate command active power-down mode entry and exit after a read command: rl = 4 (al = 1, cl =3), bl = 4 note: active power-down mode exit timing txard (?fast exit?) or txards (?slow exit?) depends on the programmed state in the mrs, address bit a12. nop nop a ctivate t0 t2 t1 cmd nop tn tn+1 cke active power-down entry nop nop act.pd 0 tis tn+2 tis active power-down exit valid command txard or txards *) ck, ck note: active power-down mode exit timing txard (?fast exit?) or txards (?slow exit?) depends on the programmed state in the mrs, address bit a12. nop nop read t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 cl = 3 cmd dq d q s, d q s nop nop nop nop nop nop tn tn+1 cke al = 1 active power-down entry rl + bl/2 nop nop act.pd 1 tis tn+2 tis active power-down exit valid command txard or txards *) ck, ck read w/ap
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 57 rev. 1.02 may 2004 active power-down mode entry and exit after a write command: wl = 2, twtr = 2, bl = 4 active power-down mode entry and exit after a write command with ap: wl = 2, twr = 3, bl = 4 note: active power-down mode exit timing txard (?fast exit?) or txards (?slow exit?) depends on the programmed state in the mrs, address bit a12. nop nop write t0 t2 t1 t3 t4 t5 t6 t7 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke wl = rl - 1 = 2 wl + bl/2 + twtr nop nop act.pd 2 twtr tis tn+2 tis valid command active power-down exit txard or txards *) ck, ck din a0 din a1 din a2 din a3 active power-down entry note: active power-down mode exit timing txard (?fast exit?) or txards (?slow exit?) depends on the programmed state in the mrs, address bit a12.wr is the programmed value in the mrs mode register. nop nop write w/ap t0 t2 t1 t3 t4 t5 t6 t7 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke wl = rl - 1 = 2 wl + bl/2 + wr nop nop act.pd 3 wr tis tn+2 tis valid command active power-down exit txard or txards *) ck, ck din a0 din a1 din a2 din a3 active power-down entry
page 58 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram precharge power down mode entry and exit auto-refresh command to power-down entry mrs, emrs command to power-down entry txp nop nop precharge *) t0 t2 t1 cmd nop nop tn tn+1 cke precharge power-down entry nop nop prepd tis tn+2 tis precharge power-down exit v alid command trp nop t3 *) "precharge" may be an external command or an internal precharge following write with ap. ck, ck t0 t2 t1 t3 t4 tn cmd cke ck, ck auto refresh arpd trfc tis txp valid command cke can go low one clock after an auto-refresh command when trfc expires the dram is in precharge power-down mode t0 t2 t1 t3 t4 t5 t6 t7 cmd cke ck, ck mrs or emrs mrs_pd t mrd enters precharge power-down mode
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 59 rev. 1.02 may 2004 2.11 no operation command 2.11.1 no operation command (nop) the no operation command should be used in cases when the sdram is in a idle or a wait state. the purpose of the no operation command is to prevent the sdram from registering any unwanted commands between opera- tions. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 2.11.2 deselect command (desel) the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t care. 2.12 input clock frequency change during operation the dram input clock frequency can be changed under the following conditions: a) during self-refresh operation b) dram is in precharge power-down mode and odt is completely turned off. the ddr2-sdram has to be in precharged power-down mode and idle. odt must be already turned off and cke must be at a logic ?low? state. after a minimum of two clock cycles after trp and taofd have been satisfied the input clock frequency can be changed. a stable new clock frequency has to be provided, before cke can be changed to a ?high? logic level again. after txp has been satisfied a dll reset command via emrs(1) has to be issued. during the following dll re-lock period of 200 clock cycles, odt must remain off. after the dll-re-lock period the dram is ready to operate with the new clock frequency. example: input frequency change during precharge power-down mode nop nop t0 t2 t1 t3 t4 tx tx+1 ty nop nop nop nop nop dll reset ty+2 ty+3 frequency change occurs here nop nop frequ.ch. tz txp stable new clock before power-down exit trp taofd minimum 2 clocks required before changing the frequency ty+1 nop valid comman d 200 clocks odt is off during dll reset
page 60 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 2.13 asynchronous ck e low reset event in a given system, asynchronous reset event can occur at any time without prior knowledge. in this situation, memory controller is forced to drop cke asynchronously low, immediately interrupting any valid operation. dram requires cke to be maintained ?high? for all valid operations as defined in this data sheet. if cke asynchronously drops ?low? during any valid operation dram is not guaranteed to preserve the contents of the memory array. if this event occurs, the memory controller must satisfy a time delay (t delay ) before turning off the clocks. stable clocks must exist at the input of dram before cke is raised ?high? again. the dram must be fully re-initialized as described the initialization sequence (section 2.2.1, step 4 thru 13). dram is ready for normal operation after the initialization sequence. see ac timing parametric table for t delay specification. asynchronous cke low event cke cke drops low due to an asynchronous reset event clocks can be turned off after this point tdelay ck, ck stable clocks
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 61 rev. 1.02 may 2004 3. truth tables 3.1 command truth table function cke cs ras cas we ba0 ba1 a12-a11 a10 a9 - a0 notes previous cycle current cycle (extended) mode register set h h llllba op code 1, 2 auto-refresh h h lllhx x x x 1 self-refresh entry h l lllhx x x x 1 self-refresh exit l h hxxxx x x x 1 single bank precharge hhllhlbaxlx1,2 precharge all banks hhllhlxxhx1 bank activate h h l l h h ba row address 1, 2 write h h l h l l ba column l column 1,2,3 write with auto-precharge h h l h l l ba column h column 1,2,3 read h h l h l h ba column l column 1,2,3 read with auto-precharge h h l h l h ba column h column 1,2,3 no operation hxlhhhxxxx1 device deselect h x hxxxx x x x 1 power down entry hl hxxx xxxx1,4 lhhh power down exit lh hxxx xxxx1,4 lhhh 1. all ddr2 sdram commands are defined by states of cs , we , ras , cas , and cke at the rising edge of the clock. 2. bank addresses (bax) determine which bank is to be operated upon. for (e)mrs bax selects an (extended) mode register. 3. burst reads or writes at bl = 4 cannot be terminated. s ee sections ?reads interrupted by a read? and ?writes inter- rupted by a write? in section 2.4.6 for details. 4. the power down mode does not perform any refresh operations. the duration of po wer down is therefore limited by the refresh requirements outlined in section 2.7. 5. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 6. ?x? means ?h or l (but a defined logic level)?. 7. operation that is not specified is illegal and after su ch an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the spec ified initialization sequence before normal operation can continue.
page 62 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 3.2 clock enable (cke) truth table for synchronous transitions current state 2 cke command (n) 3,12 ras , cas , we , cs action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power-down ll x maintain power-down 11, 13, 15 l h deselect or nop power-down exit 4, 8, 11, 13 self refresh ll x maintain self refresh 11, 15 l h deselect or nop self refresh exit 4, 5, 9 bank(s) active h l deselect or nop active power-down entry 4,8,10,11, 13 all banks idle h l deselect or nop precharge power-down entry 4,8,10,11 h l autorefresh self refresh entry 6, 9, 11, 13 any state other than listed above hh refer to the command truth table 7 1. cke (n) is the logic state of cke at clock edge n; ck e (n-1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n). 4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. on self refresh exit deselect or nop commands mu st be issued on every clock edge occurring during the txsnr period. read commands may be issued only after txsrd (200 clocks) is satisfied. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. valid commands for power-down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselct only. 10. power-down and self refresh can not be entered while read or write operations, (extended) mode register operations, precharge or refresh operations are in progress. see section 2.8 ?power down? and section 2.7.2 ?self refresh com- mand? for a detailed list of restrictions. 11. minimum cke high time is 3 clocks, minimum cke low time is 3 clocks. 12. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 13. the power-down mode does not perform any refresh operations. t he duration of power-down mode is therefor limited by the refresh requirements. 14. cke must be maintained high while the device is in ocd calibration mode. 15. ?x? means ?don?t care (including floating around vref)? in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). 16. operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3.3 data mask (dm) truth table name (function) dm dqs notes write enable l valid 1 write inhibit h x 1 1. used to mask write data; provided coincident with the corresponding data.
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 63 rev. 1.02 may 2004 4. operating conditions 4.1 absolute maximum ratings 4.2 dram component operating temperature range symbol parameter rating units notes vdd voltage on vdd pin relative to vss -1.0 to + 2.3 v 1 vddq voltage on vddq pin relative to vss -0.5 to + 2.3 v 1 vddl voltage on vddl pin relative to vss -0.5 to + 2.3 v 1 v in , v out voltage on any pin relative to vss -0.5 to + 2.3 v 1 t stg storage temperature -55 to + 100 c 1, 2 1. stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditi ons above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. symbol parameter rating units notes t oper operating temperature 0 to 95 o c 1 ~ 4 1. operating temperature is the case surface temperature on t he center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51-2. 2. the operating temperature range are the temperatures where all dram specificati on will be supported. during operation, the dram case temperature must be maintained between 0 - 95 o c under all other specification parameters. 3. some application may require to operate the dram up to 95 o c case temperature. in this case above 85 o c case temperature the auto-refresh command interval has to be reduced to trefi = 3.9 s. 4. self-refresh period is hard-coded in the chip and therefore it is imperative that the system ensures the dram is below 85 o c case temperature before initiating self-refresh operation.
page 64 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 5. ac & dc operating conditions 5.1 dc operating conditions 5.1.1 recommended dc operating conditions (sstl_18) 5.1.2 odt dc electrical characteristics 5.1.3 input and output leakage currents : symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v 1 vdddl supply voltage for dll 1.7 1.8 1.9 v 1 vddq supply voltage for output 1.7 1.8 1.9 v 1 vref input reference voltage 0.49 * vddq 0.5 * vddq 0.51 * vddq v 2, 3 vtt termination voltage vref - 0.04 vref vref + 0.04 v 4 1. vddq tracks with vdd, vdddl tracks with vdd. ac parameters are measured with vdd, vddq and vdddl tied together. 2. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting device and vref is expected to track variations in vddq. 3. peak to peak ac noise on vref may not exceed +/- 2% vref (dc). 4. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set eq ual to vref and must track variations in die dc level of vref. parameter / condition symbol min. nom. max. units notes rtt (eff) impedance value for emrs(1)(a6,a2)=0,1; 75 ohm rtt1 (eff) 60 75 90 ? 1 rtt (eff) impedance value for emrs(1)(a6,a2)=1,0; 150 ohm rtt2 (eff) 120 150 180 ? 1 deviation of vm with respect to vddq / 2 delta vm - 6.00 + 6.00 % 2 1) measurement definition for rtt(eff): apply vih (ac) and vil (ac) to test pin separately, then measure current (vihac) and (vilac) respectively. rtt(eff) = (vih (ac) - vil (ac) ) /( (vihac) - (vilac)) 2) measurement definition for vm: measure voltage (vm) at test pin (midpoint) with no load: delta vm =((2* vm / vddq) - 1) x 100% symbol parameter / condition min. max. units notes i il input leakage current; any input 0v < v in < vdd -2 +2 ? 1 i ol output leakage current; 0v < v out < vddq -5 +5 ? 2 notes: 1) all other pins not under test = 0v 2) dq?s, dqs, dqs and odt are disabled
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 65 rev. 1.02 may 2004 5.2 dc & ac logic input levels ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at vref. in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinc- tion in timing methods is verified by design and characterization but not subject to production test. in single ended mode, the dqs (and rdqs ) signals are internally disabled and don?t care. 5.2.1 single-ended dc & ac logic input levels 5.2.2 single-ended ac input test conditions symbol parameter min. max. units vih (dc) dc input logic high vref + 0.125 vddq + 0.3 v vil (dc) dc input low - 0.3 vref - 0.125 v vih (ac) ac input logic high vref + 0.250 - v vil (ac) ac input low -vref - 0.250v symbol condition value units notes vref input reference voltage 0.5 * vddq v 1, 2 vswing(max) input signal maximum peak to peak swing 1.0 v 1, 2 slew input signal minimum slew rate 1.0 v / ns 3, 4 1. this timing and slew rate definition is valid for all single-ended signals except tis, tih, tds, tdh. 2. input waveform timing is referenced to the input signal crossing through the vref level applied to the device under test. 3. the input signal minimum slew rate is to be maintained over the range from vil(dc)max to vih(ac)min for rising edges and the range from vih(dc)min to vil(ac)max for falling edges as shown in the below figure. 4. ac timings are referenced with input waveforms switching fr om vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions. v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v swing(max) delta tr delta tf start of falling edge input timing start of rising edge input timing v ih (dc) min - v il(ac) max delta tf falling slew = rising slew = v ih(ac) min - v il(dc) max delta tr
page 66 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 5.2.3 differential dc and ac input and output logic levels symbol parameter min. max. units notes vin(dc) dc input signal voltage -0.3 vddq + 0.3 1 vid(dc) dc differential input voltage 0.25 vddq + 0.6 2 vid(ac) ac differential input voltage 0.5 vddq + 0.6 v 3 vix(ac) ac differential cross point input voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 4 vox(ac) ac differential cross point output voltage 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 5 notes: 1) vin(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs etc. 2) vid(dc) specifies the input differential voltage vtr - vcp requi red for switching. the minimum value is equal to vih(dc) - v il(dc). 3) vid(ac) specifies the input differential voltage vtr - vcp requi red for switching. the minimum value is equal to vih(ac) - v il(ac). 4) the value of vix(ac) is expected to equal 0.5 x vddq of t he transmitting device and vix(ac) is expected to track variations in vddq. vix(ac) indicates the voltage at which differential input signals must cross. 5) the value of vox(ac) is expected to equal 0.5 x vddq of the transmitting device and vox(ac) is expected to track variations in vddq. vox(ac) indicates the voltage at which differential input signals must cross. crossing point vddq vssq vid vix or vox vtr vcp sstl18_3
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 67 rev. 1.02 may 2004 5.3 output buffer levels 5.3.1 sstl_18 output dc current drive 5.3.3 ocd ?off-chip driver? default characteristics symbol parameter sstl_18 class ii units notes i oh output minimum source dc current -13.4 ma 1, 3, 4 i ol output minimum sink dc current 13.4 ma 2, 3, 4 1. vddq = 1.7 v; v out = 1.42 v. (v out -vddq) / ioh must be less than 21 ohm for values of v out between vddq and vddq - 280 mv. 2. vddq = 1.7 v; v out = 280 mv. v out / iol must be less than 21 ohm for values of vout between 0v and 280 mv. 3. the dc value of vref applied to the receiving device is set to vtt 4. the values of i oh (dc) and i ol (dc) are based on the conditions given in note 1 and 2. they are used to test drive current capa- bility to ensure vihmin. plus a noise margin and vilmax. mi nus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired dr iver operating points along 21 ohm load line to define a convenient current for measurement. 5.3.2 sstl_18 output ac test conditions symbol parameter sstl_18 class ii units notes v oh minimum required output pull-up v tt + 0.603 v 1 v ol maximum required output pull-down v tt ? 0.603 v 1 v otr output timing measurement reference level 0.5 * v ddq v 2 1. sstl_18 test load for voh and vol is different from the refe rence load described in section 8.1 of this datasheet. the sstl_18 test load has a 20 ohm series resistor additionally to the 25 ohm termination resistor into vtt. the sstl_18 definition assumes that +/- 335 mv must be developed across the effectively 25 ohm termination resistor (13.4 ma x 25 ohm = 335 mv). with an additional series resistor of 20 ohm this translates into a minimum requirement of 603 mv swing relative to vtt, at the out- put device (13.4 ma * 45 ohm) = 603 mv). 2. the vddq of the devic e under test is referenced. symbol description min. nominal max. unit notes - output impedance 12.6 18 23.4 ohms 1,2 - pull-up / pull down mismatch 0 - 4 ohms 1, 2, 3 - output impedance step size for ocd calibration 0 - 1.5 ohms 8 sout output slew rate 1.5 - 5.0 v / ns 1, 4, 5, 6, 7 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. 2) impedance measurement condition for output sour ce dc current: vddq = 1.7 v, vout = 1420 mv; (vout-vddq) / ioh must be less than 23.4 ohms for values of vout between vddq and vddq - 280 mv. impedance measurement condition for output sink dc current: vddq = 1.7 v; vout = -280 mv; vout / iol must be less than 23.4 ohms for values of vout between 0 v and 280 mv. 3) mismatch is absolute value between pull-up and pull-dow n, both are measured at same temperature and voltage. 4) slew rates measured from vil(ac) to vi h(ac) with the load specified in section 8.2. 5) the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is verified by design and characterisati on but not subject to production test. 6) dram output slew rate specification applies to 400, 533 and 667 mt/s speed bins. 7) timing skew due to dram output slew rate mis-match between dqs / dqs and associated dq?s is included in tdqsq and tqhs specifi- cation. 8) this represents the step size when the ocd is near 18 ohms at nominal conditions across al l process parameters and represent s only the dram uncertainty. a 0 ohm value (no calibration) can only be achieved if the ocd impedance is 18 +/- 0.75 ohms under nominal co ndi- tions.
page 68 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 5.4 default output v-i characteristics ddr2 sdram output driver characteristics are defined for full strength default operation as selected by the emrs(1) bits a7~a9 =?111?. figures in section 5.3.5 and 5.3.6 show the driver characteristics graphically and the tables sow the same data suitable for input into simulation tools. 5.4.1 full strength default pull-up driver characteristics pull-up driver current [ma] vo lt ag e (v ) minimum nominal default low nominal default high maximum 0.2 -8.5 -11.1 -11.8 -15.9 0.3 -12.1 -16.0 -17.0 -23.8 0.4 -14.7 -20.3 -22.2 -31.8 0.5 -16.4 -24.0 -27.5 -39.7 0.6 -17.8 -27.2 -32.4 -47.7 0.7 -18.6 -29.8 -36.9 -55.0 0.8 -19.0 -31.9 -40.8 -62.3 0.9 -19.3 -33.4 -44.5 -69.4 1.0 -19.7 -34.6 -47.7 -75.3 1.1 -19.9 -35.5 -50.4 -80.5 1.2 -20.0 -36.2 -52.5 -84.6 1.3 -20.1 -36.8 -54.2 -87.7 1.4 -20.2 -37.2 -55.9 -90.8 1.5 -20.3 -37.7 -57.1 -92.9 1.6 -20.4 -38.0 -58.4 -94.9 1.7 -20.6 -38.4 -59.6 -97.0 1.8 -38.6 -60.8 -99.1 1.9 -101.1 the driver characteristics evaluation conditions are: nominal default 25 o c (tcase), vddq = 1.8 v, typical process minimum 95 o c (tcase), vddq = 1.7v, slow-slow process maximum 0 o c (tcase). vddq = 1.9 v, fast-fast process -120 -100 -80 -60 -40 -20 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vddq to vout (v) pullup current (ma) minimum nominal default low nominal default high maximum
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 69 rev. 1.02 may 2004 5.4.2 full strength default pull-down driver characteristics pull-down driver current [ma] vo lt ag e (v ) minimum nominal default low nominal default high maximum 0.2 8.5 11.3 11.8 15.9 0.3 12.1 16.5 16.8 23.8 0.4 14.7 21.2 22.1 31.8 0.5 16.4 25.0 27.6 39.7 0.6 17.8 28.3 32.4 47.7 0.7 18.6 30.9 36.9 55.0 0.8 19.0 33.0 40.9 62.3 0.9 19.3 34.5 44.6 69.4 1.0 19.7 35.5 47.7 75.3 1.1 19.9 36.1 50.4 80.5 1.2 20.0 36.6 52.6 84.6 1.3 20.1 36.9 54.2 87.7 1.4 20.2 37.1 55.9 90.8 1.5 20.3 37.4 57.1 92.9 1.6 20.4 37.6 58.4 94.9 1.7 20.6 37.7 59.6 97.0 1.8 37.9 60.9 99.1 1.9 101.1 the driver characteristics evaluation conditions are: nominal default 25 o c (tcase), vddq = 1.8 v, typical process minimum 95 o c (tcase), vddq = 1.7v, slow-slow process maximum 0 o c (tcase). vddq = 1.9 v, fast-fast process 0 20 40 60 80 100 120 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vout to vssq (v) pulldown current (ma) minimum nominal default low nominal default high maximum
page 70 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 5.4.3 calibrated output driver v-i characteristics ddr2 sdram output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the off-chip driver (ocd) impedance adjustment. the following tables show the data in tabular format suitable for input into simulation tools. the nominal points represent a device at exactly 18 ohms. the nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). real system calibration error needs to be added to these values. it must be understood that these v-i curves are represented here or in supplier ibis models need to be adjusted to a wider range as a result of any system calibration error. since this is a system specific phenomena, it cannot be quantified here. the values in the calibrated tables represent just the dram portion of uncertainty while looking at one dq only. if the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figure. in such a situation, the timing parameters in the specifica- tion cannot be guaranteed. it is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. if this can?t be guaranteed by the system calibration proce- dure, re-calibration policy and uncertainty with dq to dq variation, it is recommended that only the default values to be used. the nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum con- ditions. if calibrated at an extreme condition, the amount of variation could be as much as from the nominal mini- mum to the nominal maximum or vice versa. full strength calibrated pull-down driver characteristics full strength calibrated pull-up driver characteristics calibrated pull-down driver current [ma] voltag e (v) nominal minimum (21 ohms) normal low (18.75 ohms) nominal (18 ohms) normal high (17.25 ohms) nominal maximum (15 ohms) 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 the driver characteristic s evaluation conditions are: nominal 25 o c (tcase), vddq = 1.8 v, typical process nominal low and nominal high 25 o c (tcase), vddq = 1.8v, any process nominal minimum 95 o c (tcase). vddq = 1.7 v, any process nominal maximum 0 o c (tcase), vddq = 1.9 v, any process calibrated pull-up driver current [ma] voltag e (v) nominal minimum (21 ohms) normal low (18.75 ohms) nominal (18 ohms) normal high (17.25 ohms) nominal maximum (15 ohms) 0.2 -9.5 -10.7 -11.4 -11.8 -13.3 0.3 -14.3 -16.0 -16.5 -17.4 -20.0 0.4 -18.3 -21.0 -21.2 -23.0 -27.0 the driver characteristic s evaluation conditions are: nominal 25 o c (tcase), vddq = 1.8 v, typical process nominal low and nominal high 25 o c (tcase), vddq = 1.8v, any process nominal minimum 95 o c (tcase). vddq = 1.7 v, any process nominal maximum 0 o c (tcase), vddq = 1.9 v, any process
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 71 rev. 1.02 may 2004 5.5 input / output capacitance 5.6 power & ground clamp v-i characteristics power and ground clamps are provided on address (a0~a12, ba0, ba1), ras , cas , cs , we , cke and odt pins. the v-i characteristics for pins with clamps is shown in the following table: symbol parameter min. max. units cck input capacitance, ck and ck 1.0 2.0 pf cdck input capacitance delta, ck and ck -0.25pf ci input capacitance, all other input-only pins 1.0 2.0 pf cdi input capacitance delta, all other input-only pins - 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs, rdqs, rdqs 3.0 4.0 pf cdio input/output capacitance delta, dq, dm, dqs, dqs, rdqs, rdqs -0.5pf voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0 0 0.1 0 0 0.2 0 0 0.3 0 0 0.4 0 0 0.5 0 0 0.6 0 0 0.7 0 0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0
page 72 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 6. idd specifications and measurement conditions 6.1 idd specifications (vddq = 1.8v 0.1v; vdd = 1.8v 0.1v, 0 o c to t casemax . ) symbol parameter/condition i/o -5 ddr2 -400 -3.7 ddr2 -533 -3 & -3s ddr2 - 667 unit max. max. max. i dd0 operating current all 50 55 60 ma i dd1 operating current all 55 60 65 ma i dd2p precharge power-down current all 4 4 4 ma i dd2n precharge standby current all 28 36 45 ma i dd2q precharge quiet standby current: all 20 25 30 ma i dd3p active power-down standby current mrs(12)=0 all131620 ma mrs(12)=1 all444 ma i dd3n active standby current all 30 35 40 ma i dd4r operating current burst read x4/x8 x16 60 70 70 80 80 90 ma i dd4w operating current burst write x4/x8 x16 70 90 85 100 100 115 ma i dd5b burst auto-refresh current (trfc=trfcmin.) all 80 85 90 ma i dd5d distributed auto-refresh current (trfc=7.8s) all 6 6 6 ma i dd6 self-refresh current for standard products all 4 4 4 ma i dd6 self-refresh current for low power products all 2 2 2 ma i dd7 operating current x4/x8 x16 125 140 135 150 145 160 ma
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 73 rev. 1.02 may 2004 6.2 idd measurement conditions (vddq = 1.8v 0.1v; vdd = 1.8v 0.1v) symbol parameter/condition i dd0 operating current - one bank active - precharge tck =tck(idd).; trc = t rc(idd); tras = trasmin( idd); cke is high, cs is high between valid commands. address and control inputs are switching; data bus inputs are switching; i dd1 operating current - one bank active - read - precharge iout = 0 ma; bl = 4, tck = tck(idd), trc = trc(idd); tras = trasmin(idd); trcd = trcd( idd), cl = cl(idd).;al = 0; cke is high, cs is high between valid commands; address bus inputs are switching, data bus inputs are switching; i dd2p precharge power-down current: all banks idle; cke is low; tck = tck(i dd).; other control and address inputs are sta- ble, data bus inputs are floating. i dd2n precharge standby current : all banks idle; cs is high; cke is high; tck = tck(i dd).; other control and address bus inputs are swichting; data bus inputs are switching. i dd2q precharge quiet standby current : all banks idle; cs is high; cke is high; tck = tck(idd).; other control and address bus inputs are stable; data bus inputs are floating. i dd3p(0) active power-down current : all banks open; tck = tck(idd).;cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?0?(fast power-down exit); i dd3p(1) active power-down current : all banks open; tck = tck(idd).;cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?1?(slow power-down exit); i dd3n active standby current : all banks open; tck = tck(idd).; tras = trasmax(idd).; trp = trp(idd)., cke is high; cs is high between valid commands; other control and address i nputs are switching; data bus inputs are switching. i dd4r operating current - burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl(idd).; tck = tck(idd).; tras = trasmax(idd)., trp = trp(idd)., cke is high, cs is high between valid commands; address inputs are switch- ing; data bus inputs are switching; iout = 0ma. i dd4w operating current - burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl(idd).; tck = tck(idd).; tras = trasmax(idd)., trp = trp(idd).;cke is high, cs is high between valid commands; address inputs are switch- ing; data bus inputs are switching; i dd5b burst auto-refresh current : tck = tck(idd); refresh command every trfc = trfc(idd) interval; cke is high, cs is high between valid commands; other control and address i nputs are switching; data bus inputs are switching. i dd5d distributed auto-refresh current : tck = tck(idd).; refresh command every trefi=7.8 s interval; cke is low and c s is high between valid commands; other control and address i nputs are switching; data bus inputs are switching i dd6 self-refresh current : cke 0.2v; external clock off, ck and ck at 0v; other control and address inputs are floating; data bus inputs are floating. i dd7 all bank interleave read current: 1. all banks interleaving reads, iout = 0 ma; bl = 4, cl=cl(idd), al = trcd(idd) -1*tck(idd); tck = tck(idd), trc = trc(idd), t rrd = trrd(idd); cke is high, cs is high between valid commands, address bus inputs are stable during deselects; data bus is switching. 2. timing pattern: - ddr2 -400 -333 : a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d - ddr2 -533 -444 : a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d - ddr2 -667 -444 : a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d - ddr2 -667 -555 : a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d 3. legend: activate, ra=read with auto-precharge, d=deselect 1. idd specifications are tested after the device is properly initialized. 2. idd parameter are specified with odt disabled. 3. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs and udqs . 4. definitions for idd: low is defined as vin <= vilac(max.); high is defined as vin >= vihac(min.); stable is defined as inputs are stable at a high or low level floating is defined as inputs are vref = vddq / 2 switching is defined as: inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer (once per clock) for dq signals not including mask or strobes. 5. timing parameter minimum and maximum values for idd current measurements are defined in the following table.
page 74 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 6.2 idd measurement conditions (cont?d) for testing the idd parameters, the following timing parameters are used: 6.3 odt (on die termination) current the odt function adds additional current consumption to the ddr2 sdram when enabled by the emrs(1). depending on address bits a6 & a2 in the emrs(1) a ?week? or ?strong? termination can be selected. the current consumption for any terminated input pin, depends on the input pin is in tri-state or driving ?0? or ?1?, as long a odt is enabled during a given period of time. odt current per terminated input pin: parameter symbol -5 ddr2 -400 -3.7 ddr2 -533 -3s ddr2 - 667 -3 ddr2 - 667 unit 3-3-3 4-4-4 5-5-5 4-4-4 cas latency cl(idd) 3 4 5 4 tck clock cycle time tck(idd) 5 3.75 3 3 ns active to read or write delay trcd(idd) 15 15 15 12 ns active to active / auto-refresh command period trc(idd) 60 60 60 57 ns active bank a to active bank b command delay 1 kb page size trrd(idd) 7.5 7.5 7.5 7.5 ns active to precharge command trasmin(idd) 45 45 45 45 ns trasmax(idd) 70000 70000 70000 70000 ns precharge command period trp(idd) 15 15 15 12 ns auto-refresh to active / auto-refresh com- mand period trfc(idd) 75 75 75 75 ns emrs(1) state min. typ. max. unit enabled odt current per dq added iddq current for odt enabled; odt is high; data bus inputs are floating iodto a6 = 0, a2 = 1 tbd. tbd. 7.5 ma/dq a6 = 1, a2 = 0 tbd. tbd. 3.75 ma/dq active odt current per dq added iddq current for odt enabled; odt is high; worst case of data bus inputs are stable or switching. iodtt a6 = 0, a2 = 1 tbd. tbd. 15 ma/dq a6 = 1, a2 = 0 tbd. tbd. 7.5 ma/dq note: for power consumption calculations the odt duty cycle has to be taken into account
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 75 rev. 1.02 may 2004 7. electrical characteristics & ac timing - absolute specification 7.1 timing parameter by speed grade - ddr2-400 & ddr2-533 (v ddq = 1.8v 0.1v; v dd = 1.8v 0.1v) (notes 1-4) symbol parameter -5 ddr2-400-333 -3.7 ddr2-533-444 unit notes min. max min. max t ac dq output access time from ck / ck - 600 + 600 -500 +500 ps t dqsck dqs output access time from ck / ck - 500 + 500 -450 +450 ps t ch ck, ck high-level width 0.45 0.55 0.45 0.55 t ck t cl ck, ck low-level width 0.45 0.55 0.45 0.55 t ck t hp clock half period min (t cl, t ch) min (t cl, t ch) 5 t ck clock cycle time cl = 3 5000 8000 5000 8000 ps 6 cl = 4 & 5 5000 8000 3750 8000 ps 6 t is address and control input setup time 350 - 250 - ps 7 t ih address and control input hold time 475 - 375 - ps 7 t ds dq and dm input setup time 150 - 100 - ps 8 t ds dq and dm input hold time 275 - 225 - ps 8 t ipw address and control input pulse width (each input) 0.6 - 0.6 - t ck t dipw dq and dm input pulse width (each input) 0.35 - 0.35 - t ck t hz data-out high-impedance time from ck / ck - tacmax - tacmax ps 9 t lz (dq) dq low-impedance time from ck / ck 2*tacmin tacmax 2*tacmin tacmax ps 9 t lz (dqs) dqs low-impedance from ck / ck tacmin tacmax tacmin tacmax ps 9 t dqsq dqs-dq skew (for dqs & associated dq signals) - 350 - 300 ps 18 t qhs data hold skew factor - 450 - 400 ps t qh data output hold time from dqs t hp -t qhs t hp -t qhs t dqss write command to 1st dqs latching transition wl-0.25 wl+0.25 wl-0.25 wl+0.25 t ck t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 - 0.35 - t ck t dss dqs falling edge to ck setup time (write cycle) 0.2 - 0.2 - t ck t dsh dqs falling edge hold time from ck (write cycle) 0.2 - 0.2 - t ck t mrd mode register set command cycle time 2 - 2 - t ck t wpre write preamble 0.25 - 0.25 - t ck t wpst write postamble 0.40 0.60 0.40 0.60 t ck 10 t rpre read preamble 0.9 1.1 0.9 1.1 t ck 9 t rpst read postamble 0.40 0.60 0.40 0.60 t ck 9 t ras active to precharge command 40 70000 45 70000 ns 11 t rc active to active/auto-refresh command period 55 - 60 - ns t rfc auto-refresh to active/auto-refresh command period 75 - 75 - ns 12 t rcd active to read or write delay (with and without auto-precharge) 15 - 15 - ns 13 t rp precharge command period 15 - 15 - ns
page 76 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram t rrd active bank a to active bank b command period x4, x8 & x16 (1k page size) 7.5 - 7.5 - ns t ccd cas a to cas b command period 2 2 t ck t wr write recovery time 15 - 15 - ns t dal auto-precharge write recovery + precharge time wr+trp - wr+trp - t ck 14 t wtr internal write to read command delay 10 - 7.5 - ns 15 t rtp internal read to precharge command delay 7.5 - 7.5 - ns t xard exit power down to any valid command (other than nop or deselect) 2-2-t ck 16 t xards exit active power-down mode to read command (slow exit, lower power) 6 - al - 6 - al - t ck 16 t xp exit precharge power-down to any valid command (other than nop or deselect) 2-2-t ck t xsrd exit self-refresh to read command 200 - 200 - t ck t xsnr exit self-refresh to non-read command trfc+10 trfc+10 ns tcke cke minimum high and low pulse width 3 3 t ck t refi average periodic refresh interval 0 o c - 85 o c -7.8-7.8s 19 85 o c - 95 o c -3.9-3.9s t oit ocd drive mode output delay 0 12 0 12 ns t delay minimum time clocks remain on after cke asynchro- nously drops low tis+tck+tih - tis+tck+tih - ns 17 timing that is not specified is illegal and after such an event , in order to guarantee proper operation, the dram must be power ed down and then restarted through the specified initializa tion sequence before normal operation can continue. 7.1 timing parameter by speed grade - ddr2-400 & ddr2-533 (v ddq = 1.8v 0.1v; v dd = 1.8v 0.1v) (notes 1-4) symbol parameter -5 ddr2-400-333 -3.7 ddr2-533-444 unit notes min. max min. max
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 77 rev. 1.02 may 2004 7.2 timing parameter by speed grade - ddr2-667 (v ddq = 1.8v 0.1v; v dd = 1.8v 0.1v) (notes 1-4) symbol parameter -3s ddr2-667-555 -3 ddr2-667-444 unit notes min. max min. max t ac dq output access time from ck / ck -450 +450 -450 +450 ps t dqsck dqs output access time from ck / ck -400 +400 -400 +400 ps t ch ck, ck high-level width 0.45 0.55 0.45 0.55 t ck t cl ck, ck low-level width 0.45 0.55 0.45 0.55 t ck t hp clock half period min (t cl, t ch) min (t cl, t ch) 5 t ck clock cycle time cl = 3 5000 8000 5000 8000 ps 6 cl = 4 5000 8000 3000 8000 ps cl = 5 3000 8000 3000 8000 ps t is address and control input setup time 150 - 150 - ps 7 t ih address and control input hold time 275 - 275 - ps 7 t ds dq and dm input setup time 50 - 50 - ps 8 t dh dq and dm input hold time 175 - 175 - ps 8 t ipw address and control input pulse width (each input) 0.6 - 0.6 - t ck t dipw dq and dm input pulse width (each input) 0.35 - 0.35 - t ck t hz data-out high-impedance time from ck / ck - tacmax - tacmax ps 9 t lz (dq) dq low-impedance time from ck / ck 2*tacmin tacmax 2*tacmin tacmax ps 9 t lz (dqs) dqs low-impedance from ck / ck tacmin tacmax tacmin tacmax ps 9 t dqsq dqs-dq skew (for dqs & associated dq signals) - 250 - 250 ps 18 t qhs data hold skew factor - 350 - 350 ps t qh data output hold time from dqs t hp -t qhs t hp -t qhs t dqss write command to 1st dqs latching transition wl-0.25 wl+0.25 wl-0.25 wl+0.25 t ck t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 - 0.35 - t ck t dss dqs falling edge to ck setup time (write cycle) 0.2 - 0.2 - t ck t dsh dqs falling edge hold time from ck (write cycle) 0.2 - 0.2 - t ck t mrd mode register set command cycle time 2 - 2 - t ck t wpre write preamble 0.35 - 0.35 - t ck t wpst write postamble 0.40 0.60 0.40 0.60 t ck 10 t rpre read preamble 0.9 1.1 0.9 1.1 t ck 9 t rpst read postamble 0.40 0.60 0.40 0.60 t ck 9 t ras active to precharge command 45 70000 45 70000 ns 11 t rc active to active/auto-refresh command period 60 - 57 - ns t rfc auto-refresh to active/auto-refresh command period 75 - 75 - ns 12 t rcd active to read or write delay (with and without auto-precharge) 15 - 12 - ns 13
page 78 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram t rp precharge command period 15 - 12 - ns t rrd active bank a to active bank b command period x4, x8 & x16 (1k page size) 7.5 - 7.5 - ns t ccd cas a to cas b command period 2 2 t ck t wr write recovery time 15 - 15 - ns t dal auto-precharge write recovery + precharge time wr+trp - wr+trp - t ck 14 t wtr internal write to read command delay 7.5 - 7.5 - ns 15 t rtp internal read to precharge command delay 7.5 - 7.5 - ns t xard exit power down to any valid command (other than nop or deselect) 2-2-t ck 16 t xards exit active power-down mode to read command (slow exit, lower power) 6 - al - 6 - al - t ck 16 t xp exit precharge power-down to any valid command (other than nop or deselect) 2-2-t ck t xsrd exit self-refresh to read command 200 - 200 - t ck t xsnr exit self-refresh to non-read command trfc+10 trfc+10 ns tcke cke minimum high and low pulse width 3 3 t ck t refi average periodic refresh interval 0 o c - 85 o c -7.8-7.8s 19 85 o c - 95 o c -3.9-3.9s t oit ocd drive mode output delay 0 12 0 12 ns t delay minimum time clocks remain on after cke asynchro- nously drops low tis+tck+tih - tis+tck+tih - ns 17 timing that is not specified is illegal and after such an event , in order to guarantee proper operation, the dram must be power ed down and then restarted through the specified initializa tion sequence before normal operation can continue. 7.2 timing parameter by speed grade - ddr2-667 (v ddq = 1.8v 0.1v; v dd = 1.8v 0.1v) (notes 1-4) symbol parameter -3s ddr2-667-555 -3 ddr2-667-444 unit notes min. max min. max
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 79 rev. 1.02 may 2004 7.3 odt ac electrical characteristics and operating conditions (all speed bins) symbol parameter / condition min. max. units notes t aond odt turn-on delay 2 2 t ck t aon odt turn-on -400 & -533 tac(min) tac(max) + 1 ns ns 20 -667 tac(min) tac(max) + 0.7 ns t aonpd odt turn-on (power-down modes) tac(min) + 2 ns 2 t ck + tac(max) + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off tac(min) tac(max) + 0.6 ns ns 21 t aofpd odt turn-off (power-down modes) tac(min) + 2 ns 2.5 t ck + tac(max) + 1 ns ns t anpd odt to power down mode entry latency 3 - t ck t axpd odt power down exit latency 8 - t ck
page 80 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 7.4 notes for electrical characteristics & ac timing 1. timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a dif- ferential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see section 8 of this datasheet. 2. the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs ,rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs / dqs , rdqs / r dqs , tis, tih, tds, tdh is vref. for tis, tih, tds, tdh input reference levels see section 8.3 of this datasheet 3. inputs are not recognized as valid until vref stabilizes. during the period before vref stabilizes, cke = 0.2 x vddq is recognized as low. 4. the output timing reference voltage level is vtt. see section 8 for the reference load for timing measurements. 5. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch. 6. for input frequency change during dram operation, see the 2.11 section of this datasheet. 7. for timing definition, slew rate and slew rate derating see section 8.3 8. for timing definition, slew rate and slew rate derating see section 8.3 9. the thz, trpst and tlz, trpre parameters are referenced to a specific voltage level, which specify when the device out- put is no longer driving (thz, trpst), or begins driving (tlz, trpre). thz and tlz transitions occur in the same access time windows as valid data transitions.these parameters are verified by design and characterization, but not subject to production test. 10. the maximum limit for this parameter is not a device limit. the device operate with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 11. tras(max) is calculated from the maximum amount of time a ddr2 device can operate without a refresh command which is equal to 9 * trefi 12. a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 13. the trcd timing parameter is valid for both activate command to read or write command with and without auto-precharge. therefore a separate parameter trap for activate command to read or write command with auto-precharge is not neces- sary anymore. 14. for each of the terms, if not already an integer, round to the next highest integer. tck refers to the application clock per iod. wr refers to the wr parameter stored in the mrs. 15. twtr is at least two clocks independent of operation frequency. 16. user can choose two different active power-down modes for additional power saving via mrs address bit a12. in ?standard active power-down mode? (mrs, a12 = ?0?) a fast power-down exit timing txard can be used. in ?low active power-down mode? (mrs, a12 =?1?) a slow power-down exit timing txards has to be satisfied. 17. the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. in case of clock fre- quency change during power-down, a specific procedure is required as describes in section 2.12. 18. consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 19. the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 o c and 95 o c. 20. odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from taond. 21. odt turn off time min. is when the device starts to turn off odt resistance odt turn off time max is when the bus is in high impedance. both are measured from taofd.
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 81 rev. 1.02 may 2004 8. reference loa ds, setup & hold timing defini tion and slew rate derating 8.1 reference load for timing measurements the figure represents the timing reference load used in defining the relevant timing parameters of the device. it is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the tim- ing reference load to a system environment. manufacturers correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. this reference load is also used for output slew rate characterization. the output timing reference voltage level for single ended signals is the crosspoint with vtt. the output timing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs ) signal. 8.2 slewrate measurements 8.2.1 output slewrate with the reference load for timing measurements output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals.for differential signals (e.g. dqs / dqs ) out- put slew rate is measured between dqs - dqs = - 500 mv and dqs - dqs = + 500 mv. output slew rate is veri- fied by design and characterisation, but not tested during production. 8.2.2 input slewrate - differential signals input slewrate for differential signals (ck / ck , dqs / dqs , rdqs / rdqs ) for rising edges are measured from f.e. ck - ck = -250 mv to ck - ck = + 500 mv and from ck - ck = +250 mv to ck - ck = - 500mv for falling edges. 8.2.3 input slewrate - single ended signals input slew rate for single ended signals (other than tis, tih, tds and tdh) are measured from dc-level to ac-level: vref -125 mv to vref + 250 mv for rising edges and from vref + 125 mv to vref - 250 mv for falling edges. for slew rate definition of the input and data setup and hold parameters see section 8.3 of this datasheet. 25 ohm vtt = vddq / 2 ck, ck dut timing reference points vddq dq dqs dqs rdqs rdqs
page 82 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 8.3 input and data setup and hold time 8.3.1 timing definition for input setup (tis) and hold time (tih) address and control input setup time (tis) is referenced from the input signal crossing at the vih(ac) level for a ris- ing signal and vil(ac) for a falling signal applied to the device under test. address and control input hold time (tih) is referenced from the input signal crossing at the vil(dc) level for a rising signal and vih(dc) for a falling signal applied to the device under test.. 8.3.2 timing definition for data se tup (tds) and hold time (tdh) data input setup time (tds) with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the vih(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the vil(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs/dqs signals must be monotonic between vil(dc)max and vih(dc)min. data input hold time (tdh) with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the vil(dc) level to the differential data strobe crosspoint for a rising signal and vih(dc) to the differential data strobe crosspoint for a fall- ing signal applied to the device under test. dqs/dqs signals must be monotonic between vil(dc)max and vih(dc)min. data input setup time (tds) with single-ended data strobe enabled mr[bit10]=1, is referenced from the input sig- nal crossing at the vih(ac) level to the data strobe crossing vref for a rising signal, and from the input signal crossing at the vil(ac) level to the single-ended data strobe crossing vref for a falling signal applied to the device under test. data input hold time (tdh) with single-ended data strobe enabled mr[bit10]=1, is referenced from the input signal crossing at the vil(dc) level to the single-ended data strobe crossing vref for a rising signal and vih(dc) to the single-ended data strobe crossing vref for a falling signal applied to the device under test. v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss t is t ih t is t ih ck ck v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss t ds t dh t ds v ref t dh dqs dqs dqs differential input waveform single-ended input waveform
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 83 rev. 1.02 may 2004 8.3.3 slew rate definition for input and data setup and hold times setup (tis & tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tis & tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?vref(dc) to ac region?, use nominal slew rate for derating value (see fig. a). if the actual signal is later than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.(see fig.b) hold (tih & tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tih & tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc to vref region?, use nominal slew rate for derat- ing value (see fig. a). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref level is used for derating value (see fig.b). setup slew rate = vil(dc)max - vil(ac)max delta tfs falling signal setup slew rate = vih(dc)min - vil(ac)min delta trs rising signal hold slew rate = vref - vil(dc)max delta trh rising signal hold slew rate = vih(dc)min - vref delta tfh falling signal setup slew rate = vref(dc) - vil(ac)max delta tfs falling signal setup slew rate = vih(ac)min - vref(dc) delta trs rising signal hold slew rate = vref(dc) - vil(dc)max delta trh rising signal hold slew rate = vih(dc)min - vref(dc) delta tfh falling signal setup slew rate = tangent line [vref(dc) - vil(ac)max] delta tfs setup slew rate = tangent line [vih(ac)min - vref(dc)] delta trs hold slew rate = tangent line [vref(dc) - vil(dc)max] delta trh hold slew rate = tangent line [vih(dc)min - vref(dc)] delta tfh falling signal falling signal rising signal rising signal fig. a fig. b v ss v il(ac) max v il(dc) max v ref v ih(dc) min v ddq v ih(ac) min delta tfs delta trh delta tfh delta trs dc to vref region vref to ac region dc to vref region vref to ac region ck, ck for tis and tih dqs, dqs for tds and tdh t is t ds t ih t dh t is t ds t ih t dh v ss v il(ac) max v il(dc) max v ref v ih(dc) min v ddq v ih(ac) min delta tfs delta trh delta tfh delta trs dc to vref region dc to vref region vref to ac region vref to ac region tangent line nominal line ck, ck for tis and tih dqs, dqs for tds and tdh t is t ds t ih t dh t is t ds t ih t dh
page 84 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 8.3.4 input setup (tis) and hold (tih) time derating table 8.3.5 data setup (tds) and hold time (tdh) derating tablefor differential dqs / dqs ck, ck differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns ? tis ? tih ? tis ? tih ? tis ? tih unit command / address slew rate 4.0 +187 +94 +217 +124 +247 +154 ps 3.5 +179 +89 +209 +119 +239 +149 ps 3.0 +167 +83 +197 +113 +227 +143 ps 2.5 +150 +75 +180 +105 +210 +135 ps 2.0 +125 +45 +155 +75 +185 +105 ps 1.5 +83 +21 +113 +51 +143 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 -11 -14 +19 +16 +49 +46 ps 0.8 -25 -31 +5 -1 +35 +29 ps 0.7 -43 -54 -13 -24 +17 +6 ps 0.6 -67 -83 -37 -53 -7 -23 ps 0.5 -110 -125 -80 -95 -50 -65 ps 0.4-175-188-145-158-115-128 ps 0.3-285-292-255-262-225-232 ps 0.25 -350 -375 -320 -345 -290 -315 ps 0.2-525-500-495-470-465-440 ps 0.15 -800 -708 -770 -678 -740 -648 ps 0.1 -1450 -1125 -1420 -1095 -1390 -1065 ps 1. for all input signals the total tis (input setup time) and tih (input hold time) required is calculated by adding the indivi dual datasheet value to the derating value listed in the previous table. 2. for slow slewrate the total setup time might be negativ (i.e. a valid input signal will not have reached vih(ac) / vil(ac) a t the time of the rising clock) a valid input signal is still requir ed to complete the transistion and reach vih(ac) / vil(ac). for s lew rates in between the values listed in the next tables, the derat ing values may be obtained by linear interpolation. these val- ues are not subject to production test. they are verified only by design and characterisation. dqs, dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh unit dq slewrate (v/ns) 2.0 +125 +45 +125 +45 +125 +45 -- ---------- ps 1.5 +83+21+83+21+83+21+95+33---------- ps 1.0 000000+12+12+24+24 -------- ps 0.9 ---11-14-11-14+1-2+13+10+25+22------ ps 0.8 -----25-31-13-19-1-7+11+5+23+17---- ps 0.7 -------31-42-19-30-7-18+5-6+17+6-- ps 0.6 ---------43-49-31-47-19-35-7-23+5-11 ps 0.5 -----------74-89-62-77-50-65-38-53 ps 0.4 -------------127-140-115-128-103-116 ps 1. for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the individual datashe et value to the der- ating value listed in the previous table. 2. for slow slewrate the total setup time might be negativ (i.e . a valid input signal will not have reached vih(ac) / vil(ac) a t the time of the ris- ing dqs) a valid input signal is still required to complete the transistion and reach vih(ac) / vil( ac). for slew rates in betw een the values listed in the next tables, the derating values may be obtained by linear interpolation. these val ues are not subject to product ion test. they are verified only by design and characterisation.
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 85 rev. 1.02 may 2004 8.4 overshoot and undershoot specification 8.4.1 ac overshoot / undershoot specification for address and control pins 8.4.2 ac overshoot / undershoot specification for clock, data, strobe and mask pins parameter ddr2 -400 ddr2 -533 ddr2 -667 units maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above vdd 0.75 0.56 0.45 v.ns maximum undershoot area below vss 0.75 0.56 0.45 v.ns parameter ddr2 -400 ddr2 -533 ddr2 -667 units maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 v maximum overshoot area above vddq 0.38 0.28 0.23 v.ns maximum undershoot area below vssq 0.38 0.28 0.23 v.ns vdd vss overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) vddq vssq overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v)
page 86 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 9. package dimensions 60 balls fbga-package 10, 5 mm x 10,0 mm mo-207 variation dj-z (x4,x8) top view (see balls through package) 6.4 8.0 10,0 10,5 0,8 0,8 0,45 + - 0,05 84 balls fbga-package 12,5 mm x 10,0 mm mo-207 variation dk-z (x16) top view (see balls through package) 6.4 11.2 12,5 10,0 0,8 0,8 0,45 + - 0,05
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 87 rev. 1.02 may 2004 10. ddr2 component nomenclature 1 infineon component prefix hyb for dram components 6 product variations 0 = standard 2 = two dies in one package 2 power supply voltage 18 = 1.8 v power supply 7 die revision a = 1st generation b = 2nd generation c = 3rd generation 3 dram technology t = ddr2 8 package type c = bga package f = bga package (lead and halogen free) 4 memory density 256 = 256 mb 512 = 512 mb 1g = 1024 mb 2g = 2048 mb 9 speed grade -5 = ddr2-400-333 -3.7 = ddr2-533-444 -3 = ddr2-667-444 -3s = ddr2-667-555 5 memory organisation 40 = x4, 4 data in/outputs 80 = x8, 8 data in/outputs 16 = x16, 16 data in/outputs 0a c - 5 1 8 t 4 0 h y b 2 5 6 1 23456789 example :
page 88 rev. 1.02 may 2004 infineon technologies hyb18t256400/800/160af 256mb ddr2 sdram 11. content 1. description 1.1 ordering information 1.2 pin description 1.3 ddr2 sdram addressing 1.4 package pinouts 1.5 input / output functional description 1.6 block diagrams 2. functional description 2.1 simplified state diagram 2.2 basic functionality 2.2.1 power-on and initialization 2.2.2 programming the mode registers 2.2.3 mode register set (mrs) 2.2.4 extended mode register set (emrs(1)) 2.2.5 extended mode register set (emrs(2)) 2.2.6 extended mode register set (emrs(3)) 2.3 off-chip driver (ocd) impedance adjustment 2.4 odt on-die active termination 2.5 bank activate command 2.6 read and write command 2.6.1 posted cas 2.6.2 burst mode operation 2.6.3 burst read operation 2.6.4 burst write operation 2.6.5 write data mask 2.6.6 burst interruption 2.7 precharge command 2.7.1 burst read operation followed by a precharge 2.7.2 burst write operation followed by a precharge 2.8 auto-precharge command 2.8.1 read with auto-precharge 2.8.2 write with auto-precharge 2.8.3 read or write to precharge command spacing summary 2.8.4 concurrent auto-precharge 2.9 refresh commands 2.9.1 auto-refresh command 2.9.2 self-refresh command 2.10 power-down 2.11 other commands 2.11.1 no operation 2.11.2 deselect 2.12 input clock frequency change 2.13 asynchronous cke low event 3. truth tables 3.1 command truth table 3.2 clock enable (cke) truth table 3.3 data mask (dm) truth table 4. operating conditions 4.1 absolute maximum ratings 4.2 dram component operating temperature range
hyb18t256400/800/160af 256mb ddr2 sdram infineon technologies page 89 rev. 1.02 may 2004 content 5. ac & dc operation conditions 5.1 dc operation conditions 5.1.1 recommended dc operation conditions 5.1.2 odt dc operation conditions 5.1.3 input and output leakage current 5.2 dc & ac logic input levels 5.2.1 single-ended dc & ac logic input levels) 5.2.2 single-ended ac input test conditions 5.2.3 differential dc and ac input and output logic levels 5.3 output buffer levels 5.3.1 output dc current drive 5.3.2 output ac test conditions 5.3.4 default output v-i characteristics 5.3.5 full strength pull-up driver characteristics 5.3.6 full strength pull-down driver characteristics 5.3.7 calibrated output driver v-i characteristics 5.4 input/output capacitances 5.5 power & ground clamp v-i characteristics 6. idd specifications 6.1 idd specifications 6.2 idd measurement conditions 6.2 odt current 7. ac timing specifications 7.1 timing parameters by speed grade - ddr2-400 & ddr2-533 7.2 timing parameters by speed grade - ddr2-667 7.3 odt ac electrical characteristics and operating conditions 7.4 notes for ac timing specifications 8. reference loads, slew rates and slew rate derating 8.1 reference load for timing measurements 8.2 output slew rate measurements 8.3 input and data setup and hold time 8.3.1 timing definition for input setup and hold time 8.3.2 timing definition for data setup and hold time 8.3.3 slew rate definition for input and data setup and hold time 8.3.4 input setup and hold time derating table 8.3.5 data setup and hold time derating table 8.4 overshoot and undershoot specification 9. package dimensions 10. ddr2 component nomenclature

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